CS535: Acceleration of Algorithms in hardware
Final Projects
Prof. Lockwood : Fall 2001

DRR Scheduling for SAR`d packets

Implement a Deficit Round Robin Scheduler which can be used to implement "fairness" for packets queued. The packets will be in Virtual Output Queues (VOQ). The user will be able to define the rates at which packets leave the queue and generate various amounts of traffic from the web. The DRR will give the ability to control the output rate of the various flows. By setting the per flow "Quantum" in the DRR we can achieve the desired level of "throughput" for each flow. This gives us the ability to set priorities to flows in the switch. Thus if we queue traffic based on the type of service rather than VOQ we can give various levels of priority i.e. in effect have QoS for different services. We also aim to make this user frienly by having the ability to change the parameters in the FIFO and the DRR dynamically using the principles of `NCHARGE`.
  • Todd Sproull: GUI/ Software
  • Sarang Dharmapurikar: VHDL/Packet Queue Maintenance
  • Praveen Krishnamurthy: VHDL/Scheduler

  • Project Page

Fair Queuing Module

The goal of best-effort connection service is to serve packets or cells according to an approximation of Generalized Processor Sharing (GPS). A simple and good approximation of GPS is weighted round-robin queuing. For this project, ATM cells will be placed in FIFO queues according to their respective VCI and transmitted according to the approximation of the GPS schedule. Additional scheduling parameters will allow for priority scheduling of certain VCI. The module developed will also have dynamic configuration options by using control cells generated from NCHARGE and the ATM switch controller.
  • Douglas Taube: Fair Queuing
  • Lou Rohan: Memory Interface and registration

  • Project Page

IDE Interface as FPX Module

The RAD FPGA has 32pins available for test purposes, which is the number of Data+Control signals in an IDE interface. We intend to implement an IDE (ATA/ATAPI 5) interface as a module in the FPX to snoop transactions that pass over an IDE bus. Essentially, this project will provide a way to observe data that passes over and IDE bus, hopefully w/o jeopardizing the bus`s signal integrity.
  • Benjamin West: Hardware design
  • Maggie Zhang: VHDL coding

  • Project Page

IPv6 Tunneling Over an IPv4 Network

We intend to develop an FPX plugin that will tunnel IPv6 packets through an IPv4 network. The plugin will reside in the switches on both ends of the tunnel. One side will package IPv6 packets into IPv4 packets and tunnel them through the IPv4 network to the other side. This side will then extract the original IPv6 packets. The plugin will also accept control cells to configure the tunnel. These control cells will contain the IPv4 address to use as the other end of the tunnel for a given IPv6 network address mask. There will also likely be some additional complicating issues to consider such as fragementation due to MTU limitations.

Motion JPEG Decoder for MMX Image Proc.

The Washington University MMX compresses video in Motion JPEG format for transmission over ATM networks, where NTSC fields are encoded as a seperate JPEG images. The input cells are formatted as AAL0 and contain RAW Color JPEG data and come in at 30 Mbps. The objective of this project is to implement a hardware/software co-design. The hardware will decompress the image by extracting the DC values and to output a thumbnail (lower resolution) uncompressed image. The thumbnail output images will be sent in a UDP packet as greyscale bitmaps to a Java Applet webpage, which will Display the images and adjust the frame rate based on the connection speed, using UDP control packets. The end result is an adaptive display rate web-cam.
  • Chris Neely: Entropy dcdr, BW Bitmap, Ctrl Cell Mgr
  • Samuel Bogale: Java Applet and Rendering

  • Project Page

Network Traffic Generator

We will implement a network hardware plugin module that generates statistical patterns of networking data. The module will allow a user to send a control cell to a FPX hardware module that specifies a type of traffic (Constant bit rate, Poisson, or bursty) and the parameters of the traffic (average rate, peak rate, mean burst length). The module, in turn, will then transmit null data packets on the link as per the given parameters. The module will run at 100 MHz and be capable of generating traffic at up to 3.2 Gigabits per second.

Optic Flow Acceleration Using FPGA HW

Optic Flow Algorithms are very useful for applications which need motion data, and object tracking. The state-of-the-art software for this type of algorithm runs at about 3 Hz. This project will endeavor to perform edge detection on incoming streaming video, and then use the resulting edge data to perform optic flow. The input to the FPX will be UDP packets that contain grayscale image data for each frame of a video stream. The output will be a UDP packet per frame (except the first) which contains a series of vectors relating to how each portion of the image changed. See the website for more details.
  • Andrew Martignoni III: Optic Flow Module
  • Nicholas Webb: Edge Filter Module

  • Project Page

Power use for numeric representation

We will be investigating power use for floating point arithmetic using a new representation for the floating point number. The motivation for this is finding a way to lower power consumption in hearing aids. We will be implementing a buffer, a FP multiplier and adder, and an FIR filter. This will take in audio in the form of FP numbers and output the filtered audio.
  • Eric Hemmeter: Data Unit- FP Mult. Accum.
  • Ed Richter: Control Unit-orchestrates FIR
  • Jason White: Conversions: int->FP->int, UPDFIFO

  • Project Page

Segmentation and Reassembly of Packets

The goal of this project is to generate a networking module that supports IP traffic on multiple flows. Our module will support traffic on up to 1024 different IP flows. Further, this module will be responsible for queuing packet segments and storing them until complete packets can be assembled. At that point, the entire packet will be transmitted along the link. Packets segments will be queued using SDRAM, and separate queues will be maintained for each possible network flow path. The queue structures can be generated using a simple singly linked list. When packets are assembled, the memory can be reclaimed and used for the next packet.
  • Matt Hampton: SAR Module
  • Steve Donahue: SAR Module
  • Ryan Castanho: Push/Pull Cell Modifications

  • Project Page

Tree-based IP packet filter

This is to be hardware implementation of our CS524 course project. The set of packet filtering rules is stored in memory as a tree structure. Each tree node containes possible action to be taken. Each tree branch containes value to compare with one in the appropriate position in the packet. If the value matches, we jump to the next node until end (NULL) node. For the purpose of this project we will mark the packet (IP TOS field) if it mathches one of the rules. The packet will be then placed in different priority queues. More about the project is on the web page.
  • Derek Chen-Becker: Tree Update Module
  • Qiheng Wang: Input Controller
  • Manoj Singla: Output Controller
  • Radivoje Todorovic: Tree Parser Module

  • Project Page

Video Scaling in Reprogrammable Hardware

In this project, we will implement a WaveVideo plugin on the FPX. In waveVideo encoding, a single frame is encoded in layers each with its own priority denoting its importance in rendering the final frame. Hence, when a waveVideo flow passes through a congested link, dropping of low priority packets will degrade the image smoothly. The project itself aims to implement a simplified version of the whole system which include, dropping algorithm, paced video queues, and threshold calculation for dropping.

Projects managed by Gradebot: (C) 1996-2001