Research Focus

• Prototyping hardware-accelerated network systems
• Enhancing security of the Internet with reconfigurable hardware
• Building alternative computation platforms to perform fine-grain, parallel computation

• 
  Stanford University - Stanford, CA
  
  • Department of Electrical Engineering
    
    • Consulting Associate Professor (full-time): January 2008 - Present
    • Visiting Associate Professor (full-time): January 2007 - December 2007
  • Research: High-Performance Networking Group: Computer Systems Laboratory
    • Manage the NetFPGA Alpha and Beta Releases
    • Research clean-slate reconfigurable networking system architectures

  • Teaching:
    • Developed and instructed NetFPGA worldwide tutorials held at Stanford University, SIGMETRICS, Sydney, Glasgow, Beijing, Bangalore, Europe, and at the SIGCOMM confernece in 2008

• 
  Washington University - St. Louis, MO
  
  • Department of Computer Science and Engineering
    
    • Associate Professor with Tenure: March 2006 - December 2007
      
    • Assistant Professor: January 2001 - March 2006
      
    • Research Assistant Professor: June 1999 - December 2000
  • Research: Applied Research Lab
    • Led the Reconfigurable Network Group, a resesearch group that prototyped network security applications using reconfigurable hardware
    • Developed the Field Programmable port Extender (FPX), a platform which allows wire-speed firewall and content-aware security systems to be readily implemented.
    • Prototyped network intrusion detection and prevention mechanisms to reduce flow of SPAM, protect against the spread of viruses, and block Denial of Service (DoS) attacks
    • Researched dynamically reconfigurable and low-power hardware
  • Research Advising and and Staff Supervision
    • On committee for 11 doctoral students (Advisor for 5)
    • On committee for 16 masters thesis/projects (Advisor for 14)
    • Supervisor for 7 undergraduate study projects
    • Supervisor for 4 staff members

    
    

  • Graduate Courses Created
    • Reconfigurable System-on-Chip Design
      • E81 CSE 566: Fall 2006 , Fall 2004 , Fall 2002
    • Acceleration of Algorithms in Reconfigurable Hardware
      • E81 CSE 565: Fall 2005 , Fall 2003 , Fall 2001
    
    
  • Graduate Research Seminars Instructed
    • Jointly instructed Research Seminar on Networking
      • CSE 770: Fall 2006, Spring 2006, Fall 2005, Spring 2005, Fall 2004
    • Created research seminars on Reconfigurable Hardware
      • CSE 681: Spring 2004, Fall 2003, Spring 2003, Fall 2002 , Spring 2002

  • Undergraduate Courses Instructed
    • Digital Computers: Switching Theory and Logic Synthesis
      • E65: CSE 460: Spring 2006, Spring 2001
    • Digital Systems Laboratory
      • E61: CSE 465 - Spring 2005
    • Processing Systems and Structures
      • E61: CS/CoE 306 - Spring 2004, Spring 2003, Spring 2002

  • Leadership
    • Center for Security Technologies
      • Leader, Advanced Electronic Systems Research Thrust.
      • Leader, High Speed Network Security Research Testbed.

  • Service
    • Computer Engineering Faculty Committee (2000 - 2007)
    • Colloquium Series Coordinator (2003 - 2005)
    • Technology Adoption Committee (2003 - 2006)
    • Internet2 Committee (2001)
• 
  University of Illinois - Champaign-Urbana, IL
  Department of Electrical and Computer Engineering
  Adjunct Professor: June 1999 - March 2001
  Visiting Assistant Professor, Dec 1995 - June 1999 (50% appointment)

  • Research: Project leader for iPOINT Network Research Projects
    • Illinois Pulsar-Based Optical Interconnect (iPOINT) Testbed
      • Prototyped input-buffered ATM switch using Field Programmable Gate Array (FPGA) devices.
      • Implemented scheduling algorithms for input-buffered switches.
    • Illinois Wireless ATM Network Development Research (iWANDeR)
      • Developed software to provide Quality of Service for last-hop wireless networks.
      • Prototyped wireless LAN services on Linux.

  • Research Supervision
    • Advisor for 1 doctoral student (completed)
    • Committee member for 2 doctoral students (completed)
    • Supervisor for 7 undergraduate study projects

  • Undergraduate Courses Instructed
    • System and Machine-level programming
      • ECE291 - Fall 1996 - Spring 1999
    • Taught students system-level programming for microprocessors
      with emphasis on code optimization, graphics, sound, and networking.
    • Developed ECE291 Gradebot: An interactive, web-based tool for
      Automated grading, gradebook maintenance, and project management.

  • Awards
    • List of Teachers Ranked as Excellent by Their Students: Spring 1998 for Fall 1997
    • List of Teachers Ranked as Excellent by Their Students: Fall 1998 for Spring 1998
    • List of Teachers Ranked as Excellent by Their Students: Fall 1999 for Spring 1999

Consulting and Industry Positions (in reverse chronological order)

• 
  Science Applications International Corporation (SAIC), Washington DC
  December 2003 - June 2006
  Consultant

• 
  Global Velocity, St. Louis, MO
  Oct. 2001 - Apr. 2005
  Co-founder, Independent Consultant, Chief Scientist

• 
  Pennie and Edmonds, LLP, New York, NY
  Oct 1999 - Jan 2002
  Expert Witness
  • Provided testimony regarding prior art in the Amazon vs. Barnes and Noble case of `One-click' (Single-action), web-based, electronic commerce system (USPTO 5,960,411).
  • Provided in-court testimony and depositions that led the US Court of Appeals for the Federal Circuit to nullify Amazon's preliminary injunction issued against Barnes and Noble.

• 
  National Center for Supercomputing Applications - Champaign, IL
  Oct 1995 - June 1999 (50% appointment)
  Senior Network Engineer with NCSA's Network Development Group.
  • Developed components of NetDocs: Interactive, web-based tools for Network Mangement
  • Authored and presented white papers and workshops on Internet, ATM, and wireless networks.
  • Helped design and maintain NCSA's ATM and switched Ethernet campus backbone.

• 
  AT&T Bell Laboratories - Murray Hill, NJ
  May 1994 - Aug 1994 & May 1993 - Aug 1993
  Consultant, Intern
  • Developed Scalable, Modular Framework to support 1:N and M:N multicast trees over AT&T's Experimental University Network (XUNET).
  • Investigated MBone-style IP multicast routing and tested IP multicast routing on the XUNET network.

• 
  International Business Machines (IBM) - Research Triangle Park, NC
  May 1991 - Aug 1991
  Hardware Engineer, Intern
  • Designed pre-emptive packet transport HDLC for T1/J1/E1 digital communication network link using Xilinx 3000-series FPGA.

Research Grants

• National Science Foundatation

  Prototype and Distribution of Reprogrammable Queuing Modules for Scalable Input Buffered Switches PI: John W Lockwood, University of Illinois and Washington University Research Contract: July 1999 - July 2003, $773,000 Software Innovations for Liquid Architectures PI: Ron Cytron, Washington University Co-PI(s): John Lockwood, Roger Chamberlain, Jason Fritts, Research Contract: Sept. 2002 - Aug. 2003, $142,113 ITR/NGS: High-Performance Configurable Hardware Using Liquid Architecture PI: Ron Cytron, Washington University Co-PIs: John Lockwood, Roger Chamberlain, Jason Fritts Research Contract: Sept. 15, 2003 - Aug 31, 2007, $512,779 STI: The Open Network Laboratory - A Resource for High Performance Networking Research PI: Jonathan Turner, Washington University Co-PI: John Lockwood Research Contract: Jan. 2003 - Dec. 2005, $1,199,999 ITR-M: Technologies for Dynamically Extensible Networks PI: Jonathan Turner, Washington University Co-PI: John Lockwood Research Contract: Jan 1, 2004 - Dec 31, 2007, $1,050,000 Virtual Networking - Enabling Network Service Innovation PI: Jonathan Turner, Washington University Co-PIs: John W. Lockwood, Patrick Crowley, Sergey Gorinsky Research Contract: Sep. 2004 - Aug. 2005, $250,000 MRI:Development of a Diversified Router for Experimental Research in Networking PI: Jonathan Turner, Washington University Co-PIs: John W. Lockwood, Patrick Crowley Research Contract: Oct 1, 2005 - Sep. 30, 2008 $800,000 CRI: Enhancing the Open Network Laboratory PI: Jonathan Turner, Washington University Co-PIs: John W. Lockwood, Patrick Crowley Research Contract: July 1, 2006 - June 30, 2008, $1,099,726 NeTS-FIND: An Architecture for a Diversified Internet PI: Jonathan Turner, Washington University Co-PIs: John W. Lockwood, Patrick Crowley, Sergey Gorinsky Research Contract: Sept. 15, 2006 - Aug 31, 2009, $1,098,974

  
  

• Science Applications International Corporation (SAIC)
  

  Fast Semantic Content Processing PI: John W Lockwood, Washington University, Co-PI: Ron Loui, Young Cho Research Contracts: Apr 2006-Feb 2007: $334,092 PI: John W Lockwood, Washington University, Co-PI: Ron Loui, Robert Pless, William Smart Research Contracts: Apr 2005-Mar 2006: $815,000

  
  
• Global Velocity

  Reprogrammable Hardware for Examination of Packet Content PI: John W Lockwood, Washington University Research Contracts: Jan 2005 - Mar 2005: $104,176 Research Contracts: Jan 2004 - Dec 2004: $458,613 Research Contracts: Jan 2003 - Dec 2003: $297,735 Research Contracts: Jan 2002 - Dec 2002: $58,071 Research Contracts: Aug 2001 - Dec 2001: $10,102

  
  
  
• Boeing

  Evaluation of QoS and Node Clustering for Large-scale Avionic Networks PI: John W. Lockwood Research Contract: Jan 2007 - Nov 2007, $119,953 Demonstration and evaluation of current NCO intelligent distributed system management PI: John W. Lockwood, Washington University Research Contract: Mar 2006 - Dec 2006, $57,000 Research Contract: Jan 2005 - Dec 2005, $148,996 Demonstration and Evaluation of Network Management Approaches PI: John W. Lockwood, Washington University Research Contract: Jan 2004 - Dec 2004, $99,999

  
  
• Agilent

  Low Power Network Measurement PI: John W Lockwood, Washington University Corporate Gift: October 2005, $53,000

  
  
• Rockwell Collins

  Intelligent Network Demonstration PI: John W Lockwood, Washington University Research Contract: May 2003 - August 2003, $23,562 Hardware Acceleration For Multiple Image Rendering PI: John W Lockwood, Washington University Corporate Gift: June 2003, $21,000

  
  
• Kauffman Foundation

  Development of entrepreneurship in academic research PI: John W Lockwood, Washington University Award Grant: May 2005 - December 2005 $24,500

  
  
• Synplicity

  Donation of Computer Aided Design (CAD) tools for CSE565 PI: John W Lockwood, Washington University Corporate Donation 15 floating licenss of Synplify Pro, Amplify, and Identify Computer Aided Design (CAD) Tools Commercial value of kind corporate gift: $1,980,000

  
  
• Xilinx

  Dynamically Reconfigurable Logic for Networking Modules PI: John W Lockwood, Washington University Corporate Gift: September 2002, $50,000 Corporate Gift: August 2001, $50,000 Corporate Gift: February 2001, $50,000 Corporate Gift: February 2000, $50,000 In-kind Award of FPGA Devices PI: John W Lockwood, Washington University Corporate Donation of FPGA Core: Nov 2006 - $25,000 Corporate Donation of FPGAs and design tools: Sep 2005 - $37,447 Corporate Donation of FPGAs: June, 2005 - $35,940 Corporate Donation of FPGAs and Kits: June, 2004 - $39,656 Corporate Donation of FPGAs and Kits: Mar, 2004 - $127,850 Corporate Donation of FPGAs: Nov, 2002 - $244,295 Corporate Donation of FPGAs: May, 2001 - $12,980 Corporate Donation of FPGAs: July, 2000 - $120,600

  
  
• Altera

  ATM Reprogrammable Queuing Modules PI: John W Lockwood, University of Illinois Corporate Gift: April 1999 - April 2000, $20,000

Patents

1. Methods and systems for content detection in a reconfigurable hardware, Bharath Madhusudan and John W. Lockwood; Filed: August 2005, USPTO: 20060053295.
2. Method and Apparatus for Detecting Predefined Signatures In Packet Payload Using Bloom Filters, Sarang Dharmapurikar, Praveen Krishnamurthy, Todd Sproull, John W. Lockwood; Filed: August 2003, USPTO: 2005008652.
3. TCP-splitter: reliable packet monitoring methods and apparatus for high speed networks, David Schuehler, John W. Lockwood; Filed: August 2002. USPTO: 20030177253.
4. Reliable Packet Monitoring Methods and Apparatus for High-Speed Networks, David Schuehler, John W. Lockwood; Filed: August 2003. USPTO: 20040049596,
5. Methods, Systems, and Devices using Reprogrammable Hardware for High-Speed Processing of Streaming Data to Find a Redefinable Pattern and Respond Thereto, John W. Lockwood, Ronald Loui, James Moscola, Michael Pachos, Filed: May 2002, Awarded: August 15, 2006. US Patent: 7,093,023
6. System and Method for Controlling Transmission of Data Packets Over an Information Network, Matthew P. Kulig, Timmy L. Brooks, John W. Lockwood, David K. Reddick; Filed: October 2001, USPTO: 20030110229.
7. Scalable broad band input-queued ATM switch including weight driven cell scheduler, H. Duan, J. W. Lockwood, and S. M. Kang, US Patent: 5,923,656 Filed October 22, 1996, Awarded July 13, 1999.

Recent Publications

Peer-reviewed, Full-length, Refereed, and Archived { Journals and Conference Papers }

(In reverse chronological order - Most recent at the top)
(Also available as BibTeX database)

1. NetFPGA-An Open Platform for Teaching How to Build Gigabit-rate Network Switches and Routers; by Glen Gibb, John W. Lockwood, Jad Naous, Paul Hartke, and Nick McKeown; To Appear: IEEE Transactions of Education, 2008.
2. Demonstration of the NetFPGA System for Gigabit-rate Routing of Streaming Internet Video; by John W. Lockwood, Nick McKeown, Glen Gibb, Jad Naous, Adam Covington; Submitted to: ACM Transactions on Design Automation of Electronic Systems (TODAES), Special Issue on Demonstrable Software Systems and Hardware Platforms; Submitted: Sep. 2007.
3. Supercharging PlanetLab - High Performance, Multi-Application, Overlay Network Platform; by Jon Turner, Patrick Crowley, John Dehart, Amy Freestone, Brandon Heller, Fred Kuhms, Sailesh Kumar, John Lockwood, Jing Lu, Mike Wilson, Charles Wiseman, Dave Zar; SIGCOMM 2007, August 27-31, Kyoto, Japan.
4. Adaptive Thermoregulation for Applications on Reconfigurable Devices, by Phillip H. Jones, James Moscola, Young H. Cho, John W. Lockwood; Proceedings of International Conference on Field-Programmable Logic and Applications (FPL), Amsterdam, Netherlands, August 27-29, 2007.
5. Prototyping Fast, Simple, Secure Switches for Ethane, Jianying Luo, Justin Pettit, Martin Casado, Nick McKeown, John Lockwood; IEEE Symposium on High Performance Interconnects (Hot Interconnects-15), Stanford, CA, August 22-24, 2007.
6. Empirical Performance Assessment Using Soft-Core Processors on Reconfigurable Hardware, by Richard Hough, Praveen Krishnamurthy, Roger D. Chamberlain, Ron K. Cytron, John Lockwood, and Jason Fritts, in ACM FCRC: Workshop on Experimental Computer Science, San Diego, CA; June 13-14, 2007.
7. Sensitivity Analysis of Gigabit Concept Mining System; by Andrew Levine, Ron Loui, John W. Lockwood, Young H. Cho; IEEE Aerospace Conference; Big Sky, MT; March 3-10, 2007; Paper 10.0801.
8. Hardware-Accelerated Parser for Extraction of Metadata in Semantic Network Content; by James Moscola, Young H. Cho, John W. Lockwood; IEEE Aerospace Conference; Big Sky, MT, March 3-10, 2007, Paper 10.0702.
9. Streaming Hierarchical Clustering for Concept Mining; by Moshe Looks, Andrew Levine, G. Adam Covington, Ronald P. Loui, John W. Lockwood, Young H. Cho; IEEE Aerospace Conference; Big Sky, MT, March 3-10, 2007; Paper 10.0701
10. Management and Service Discovery in Satellite and Avionic Networks; by Todd Sproull, John W. Lockwood, John Meier; IEEE Aerospace Conference; Big Sky, MT; March 3-10, 2007; Paper 10.1501
11. Dynamic Optimization of Workload for FPGA Application using Thermal Measurements, by Phillip H. Jones, Young H. Cho, and John W. Lockwood, 20th IEEE/ACM International Conference on VLSI Design, Bangalore, India, January 6-10, 2007.
12. An Adaptive Frequency Control Method Using Thermal Feedback for Reconfigurable Hardware Applications, by Phillip Jones, Young Cho, John Lockwood, IEEE International Conference on Field Programmable Technology (FPT), Bangkok, Thailand, Dec 13-15, 2006.
13. Fast Packet Classification Using Bloom Filters, by Sarang Dharmapurikar, Haoyu Song, Jonathan Turner, John Lockwood, ACM Symposim on Architectures for Networking and Communications Systems (ANCS), San Jose, CA, Dec 4-5, 2006
14. Fast and Scalable Pattern Matching for Network Intrusion Detection Systems, by Sarang Dharmapurikar and John W. Lockwood, IEEE Journal on Selected Areas in Communications, (JSAC) Oct. 2006, Volume: 24, Issue: 10, pp. 1781- 1792
15. A Thermal Management and Profiling Method for Reconfigurable Hardware Applications; by Phillip H. Jones, John W. Lockwood, Young H. Cho; 16th Annual Conference on Field Programmable Logic and Applications (FPL); Madrid, Spain, August 28-30, 2006; pp. 103-109.
16. High Speed Document Clustering in Reconifigurable Hardware; by G. Adam Covington, Charles L.G. Comstock, Andrew A. Levine, John W. Lockwood, Young H. Cho; 16th Annual Conference on Field Programmable Logic and Applications (FPL); Madrid, Spain, August 28-30, 2006; pp. 411-417.
17. A Reconfigurable Architecture for Multi-Gigabit Speed Content-Based Routing, by James Moscola, Young H. Cho, and John W. Lockwood, IEEE Symposium on High Performance Interconnects (Hot Interconnects-14), Stanford, CA, August 23-24, 2006, pp. 61-66.
18. Rethinking Hardware Support for Network Analysis and Intrusion Prevention, Vern Paxson, Krste Asanovic, Sarang Dharmapurikar, John Lockwood, Ruoming Pang, Robin Sommer, Nick Weaver; USENIX First Workshop on Hot Topics in Security (HotSec), Vancouver, B.C., July 31, 2006.
19. Automatic Application-Specific Microarchitecture Reconfiguration; by Shobana Padmanabhan, Ron K. Cytron, Roger D. Chamberlain and John W. Lockwood; 13th Reconfigurable Architectures Workshop (RAW), Apr 25-26, 2006
20. Context-Free Grammar based Token Tagger in Reconfigurable Devices, by Young H. Cho, James Moscola, John W. Lockwood; Proceedings of International Workshop on Data Engineering (ICDE/SeNS), Atlanta, GA, April 3-7, 2006.
21. Hardware Accelerated Algorithms for Semantic Processing of Document Streams, by John W. Lockwood, Stephen G. Eick, Justin Mauger, John Byrnes, Ron Loui, Andrew Levine, Doyle J. Weishar, Alan Ratner, IEEE Aerospace Conference, Big Sky, MT, March 4-11, 2006, Paper 10.0802
22. Cycle-Accurate Microarchitecture Performance Evaluation, by Richard Hough, Phillip Jones, Scott Friedman, Roger Chamberlain, Jason Fritts, John Lockwood, and Ron Cytron, In Proceedings of Workshop on Introspective Architecture, Austin, TX, February 2006.
23. Multi-pattern Signature Matching for Hardware Network Intrusion Detection Systems, by Haoyu Song and John W. Lockwood, IEEE Globecom 2005, St. Louis, MO, Nov. 28, 2005, pp. CN-02-3.
24. Optimizing Memory Bandwidth of a Multi-Channel Packet Buffer, by Sarang Dharmapurikar, Sailesh Kumar, John W. Lockwood, and Patrick Crowley; IEEE Globecom 2005, St. Louis, MO, Nov. 28, 2005, pp. CG-3-8.
25. Shape Shifting Tries for Faster IP Route Lookup, by Haouy Song, Jonathan Turner and John Lockwood. Proceedings of the IEEE International Conference on Network Protocols (ICNP), Boston, MA, Nov. 6, 2005, pp. 358-367.
26. Fast and Scalable Pattern Matching for Content Filtering, Sarang Dharmapurikar, John Lockwood Proceedings of Symposium on Architectures for Networking and Communications Systems (ANCS), Princeton, NJ, Oct 2005.
27. Fast Hash Table Lookup Using Extended Bloom Filter: An Aid to Network Processing, by Haoyu Song, Sarang Dharmapurikar, Jonathan Turner, John Lockwood; ACM SIGCOMM; Philadelphia, PA; August 21-26, 2005.
28. HAIL: A Hardware-Accelerated Algorithm for Language Identification; by Charles M. Kastner, G. Adam Covington, Andrew A. Levine, John W. Lockwood; 15th Annual Conference on Field Programmable Logic and Applications (FPL); Tampere, Finland; August 24-26, 2005.
29. SIFT: Snort Intrusion Filter for TCP; by Michael Attig and John W. Lockwood; IEEE Symposium on High Performance Interconnects (Hot Interconnects-13); Stanford, CA; August 17-19, 2005.
30. Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures, by Shobana Padmanabhan, Phillip Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood; International Journal of Parallel Programming, volume 33, number 2-3, June 2005, pages 115-136.
31. A Framework For Rule Processing in Reconfigurable Network Systems; by Michael E. Attig and John W. Lockwood, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM); Napa, CA; April 17-20, 2005. [Slides]
32. IPSec Implementation on Xilinx Virtex-II Pro FPGA and Its Application, by Jing Lu and John Lockwood, Reconfigurable Architectures Workshop (RAW), Denver, Colorado, April 5, 2005.
33. Transformation Algorithms for Data Streams, by John W. Lockwood, Stephen G. Eick, Doyle J. Weishar, Ron Loui, James Moscola, Chip Kastner, Andrew Levine, Mike Attig, IEEE Aerospace Conference, Big Sky, Montana, March 2005.
34. Efficient Packet Classification for Network Intrusion Detection using FPGA, by Haoyu Song and John W. Lockwood, International Symposium on Field-Programmable Gate Arrays (FPGA'05), Monterey, California, Feb 20-22, 2005. [Slides]
35. A Hardware-Accelerated System for Real-Time Worm Detection, by Bharath Madhusudan and John W. Lockwood, IEEE Micro, January 2005, Vol. 25, No. 1, pp. 60-69
36. Wide-area Hardware-accelerated Intrusion Prevention Systems (WHIPS), by Todd Sproull and John Lockwood, International Working Conference on Active Networking (IWAN), October 27-29, 2004, Lawrence, Kansas, USA.
37. A Modular System for FPGA-based TCP Flow Processing in High-Speed Networks; by David Schuehler, John Lockwood; 14th International Conference on Field Programmable Logic and Applications (FPL), Springer LNCS 3203, Antwerp, Belgium, August 2004, pp. 301-310.
38. Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs; by Edson Horta and John W. Lockwood; 14th International Conference on Field Programmable Logic and Applications (FPL), Springer LNCS 3203, Antwerp, Belgium, August 2004, pp. 975-979.
39. Design of a System for Real-Time Worm Detection, by Bharath Madhusudan and John Lockwood; 12th Annual Proceedings of IEEE Hot Interconnects (HotI-12); Stanford, CA, August, 2004, pp. 77-83.
40. Deep Packet Inspection using Parallel Bloom Filters, by Sarang Dharmapurikar, Praveen Krishnamurthy, Todd S. Sproull, John W. Lockwood; IEEE Micro, Vol. 24, No. 1, Jan 2004, pp. 52-61
41. Architecture for a Hardware-Based, TCP/IP Content-Processing System, by David V. Schuehler, James Moscola, John W. Lockwood; IEEE Micro, Vol. 24, No. 1, Jan 2004, pp. 62-69
42. Application of Hardware Accelerated Extensible Network Nodes for Internet Worm and Virus Protection, by John W. Lockwood, James Moscola, David Reddick, Matthew Kulig, and Tim Brooks, International Working Conference on Active Networks (IWAN), Kyoto, Japan, December, 2003.
43. System-on-Chip Packet Processor for an Experimental Network Services Platform, by David Taylor, Alex Chandra, Yuhua Chen, Sarang Dharmapurikar, John Lockwood, Wenjing Tang, Jonathan Turner; Proceedings of IEEE Globecom 2003, December 2003.
44. Internet Worm and Virus Protection in Dynamically Reconfigurable Hardware; by John W. Lockwood, James Moscola, Matthew Kulig, David Reddick, Tim Brooks, Military and Aerospace Programmable Logic Device (MAPLD), Washington DC, 2003, Paper E10, Sep 9-11, 2003. [Photos]
45. An Extensible, System-On-Programmable-Chip, Content-Aware Internet Firewall, by John W. Lockwood, Christopher Neely, Christopher Zuver, James Moscola, Sarang Dharmapurikar, and David Lim; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, pp. 859-868 (Paper 14B), Sep 1-3, 2003.
46. A TCP/IP Based Multi-Device Programming Circuit, by David V. Schuehler, Harvey Ku, John Lockwood; Field Programmable Logic and Applications (FPL), Lisbon, Portugal, Paper P2.B, Sep 1-3, 2003.
47. Deep Packet Inspection Using Parallel Bloom Filters, by Sarang Dharmapurikar, Praveen Krishnamurthy, Todd Sproull, John W. Lockwood; Symposium on High Performance Interconnects (HotI), Stanford, CA, USA, pp. 44-51, Aug. 20-22, 2003.
48. Architecture for a Hardware Based, TCP/IP Content Scanning System, by David V. Schuehler, James Moscola, and John W. Lockwood; Symposium on High Performance Interconnects (HotI), Stanford, CA, USA, pp. 89-94, Aug. 20-22, 2003.
49. Implementation of a Streaming Content Search-and-Replace Module for an Internet Firewall, by James Moscola, Michael Pachos, John W. Lockwood, Ron P. Loui; Symposium on High Performance Interconnects (HotI), Stanford, CA, USA, pp. 122-129, Aug 20-22, 2003.
50. Automated Tools to Implement and Test Internet Systems in Reconfigurable Hardware, by John W. Lockwood, Chris Neely, Chris Zuver, Dave Lim; SIGCOMM Computer Communications Review (CCR), vol 33, no 3, July 2003, pp 103-110.
51. Scalable IP Lookup for Internet Routers, by David E. Taylor, Jonathan S. Turner, John W. Lockwood, Todd S. Sproull, David B. Parlour, IEEE Journal on Selected Areas in Communications (JSAC), Vol. 21, No. 4, May 2003, pp. 522-534.
52. Implementation of a Content-Scanning Module for an Internet Firewall, James Moscola, John Lockwood, Ronald P. Loui, Michael Pachos; Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 9-11, 2003. [Presentation], [Demo Night Photos], [Audience Photos]
53. TCP Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware, David V. Schuehler, John W. Lockwood; IEEE Micro, Vol. 23, No. 1, Jan. 2003, pp. 54-59.
54. Power Consumption of Customized Numerical Representations for Audio Signal Processing, by Roger Chamberlain, Yen Hsiang Chew, Vuruna DeAlwis, Eric Hemmeter, John Lockwood, Robert Morley, Ed Richter, Jason White, and Huakai Zhang, Sixth Annual Workshop on High Performance Embedded Computing (HPEC), Massachusetts Institute of Technology Lincoln Laboratory, September 24-26, 2002.
55. Using PARBIT to implement Partial Run-Time Reconfigurable Systems, by Edson L. Horta, John W. Lockwood, and Sergio T. Kofuji, International Conference on Field Programmable Logic and Applications (FPL), Montpellier, France, September 2-4, 2002, Paper 5A.4.
56. TCP-Splitter: A TCP/IP Flow Monitor in Reconfigurable Hardware, by David V. Schuehler, John Lockwood; Proceedings of Hot Interconnects 10 (HotI-10), Stanford, CA, August 21-23, 2002, pp. 127-131.
57. Implementing a dynamically reconfigurable ATM switch on the VIRTEX FPGA of the FPX platform, by Edson L. Horta, John W. Lockwood, Sergio T. Kofuji; Proceedings of SPIE, volume 4867, Boston, MA, July 30 2002.
58. Scalable IP Lookup for Programmable Routers, by David E. Taylor, John W. Lockwood, Todd S. Sproull, Jonathan S. Turner, David B. Parlour; IEEE Infocom 2002, New York NY, June 23-27, 2002.
59. Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration. by Edson L. Horta, John W. Lockwood, David E. Taylor, David Parlour; Design Automation Conference (DAC), New Orleans, LA, June 10-14, 2002, Paper 24.2.
60. Design of a High Performance Dynamically Extensible Router, by Fred Kuhns, John DeHart, Anshul Kantawala, Ralph Keller, John Lockwood, Prashanth Pappu, Jyoti Parwatikar, Ed Spitznagel, David Richards, David Taylor, Jon Turner, Ken Wong; DARPA Active Networks Conference and Exposition (DANCE), May 29-31 2002, San Francisco, CA.
61. Control and Configuration Software for a Reconfigurable Networking Hardware Platform, by Todd Sproull, John W. Lockwood, David E. Taylor; IEEE Symposium on Field-Programmable Custom Computing Machines, (FCCM), Napa, CA, April 24, 2002. [Photos]
62. Protocol Wrappers for Layered Network Packet Processing in Reconfigurable Hardware, by Florian Braun, John Lockwood, and Marcel Waldvogel; IEEE Micro, Volume 22, Number 3, Feb 2002, pp. 66-74.
63. A Resource-based Approach to MAC Layer Independent Hierarchical Link-Sharing in Wireless Local Area Networks, by Lars Wischhof and John Lockwod; European Wireless 2002 (EW2002), Feb 2002, Florence, Italy.
64. Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance Programmable Routers, by David E. Taylor, Jonathan S. Turner, John W. Lockwood, Edson L. Horta; Computer Networks, February 2002, Volume 38, Issue 3, pp. 295-310, Elsevier Science.
65. Wireless call admission control using threshold access sharing, by Jay R. Moorman and John W. Lockwood; IEEE Global Telecommunications Conference (GLOBECOM 2001), Vol. 6, San Antonio, TX, November 25-29, 2001, pp. 3698 - 3703.
66. Reconfigurable router modules using network protocol wrappers, by Florian Braun, John Lockwood, Marcel Waldvogel; FPL 2001, Belfast, Northern Ireland, UK, August 28, 2001. pp. 254-263.
67. Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware, by Florian Braun, John Lockwood, Marcel Waldvogel; Proceedings of Hot Interconnects 9 (HotI-9), Stanford, CA, Aug 22-24, 2001, pp. 93-98.
68. Evolvable Internet Hardware Platforms, by John W. Lockwood, NASA/DoD Workshop on Evolvable Hardware (EHW'01), Long Beach, CA, July 12-14, 2001, pp. 271-279.
69. Dynamic Hardware Plugins (DHP): Exploiting Reconfigurable Hardware for High-Performance in Programmable Routers, by David E. Taylor, Jonathan S. Turner, John W. Lockwood; IEEE OPENARCH 2001: 4th IEEE Conference on Open Architectures and Network Programming, Anchorage, AK, April 2001.
70. Reprogrammable Network Packet Processing on the Field Programmable Port Extender (FPX), by John W. Lockwood, Naji Naufel, Jon S. Turner, and David E. Taylor; ACM International Symposium on Field Programmable Gate Arrays (FPGA'2001), Monterey, CA, February 2001, pp. 87-93.
71. An Open Platform for Development of Network Processing Modules in Reprogrammable Hardware, by John W. Lockwood; IEC DesignCon 2001, Santa Clara, CA, Jan. 2001, Paper WB-19.
72. Compensation Modeling for QoS Support on a Wireless Networks by Stefan Bucheli, Jay Moorman, John Lockwood, and Steve Kang: IEEE Global Telecommunications Conference (GLOBECOM 2000), November, 2000, San Francisco, CA.
73. Real-Time Prioritized Call Admission Control in a Base Station Scheduler. by Jay Moorman, John Lockwood, and Steve Kang. IEEE/ACM Wowmom, August, 2000. Boston, MA.
74. Experimentation and Analysis for Unified Packet-based Wireless Networks, by Jay Moorman and John Lockwood, IEEE 3G Wireless, June, 2000. San Francisco, CA, pgs. 239-245.
75. Field Programmable Port Extender (FPX) for Distributed Routing and Queuing, by John W. Lockwood, Jon S. Turner, David E. Taylor; ACM International Symposium on Field Programmable Gate Arrays (FPGA'2000), Monterey, CA, February 2000, pp. 137-144.
76. Implementation of the Multiclass Priority Fair Queuing (MPFQ) Algorithm for Extending Quality of Service in Existing Backbones to Wireless Endpoints. by Jay Moorman and John Lockwood; IEEE Global Telecommunications Conference (GLOBECOM 1999), Rio De Janeiro, Brazil, December, 1999. Pgs. 2752-2757.
77. Design of a Flexible Open Platform for High Performance Active Networks, by Sumi Choi, John Dehart, Ralph Keller, John Lockwood, Jonathan Turner and Tilman Wolf; Allerton Conference, Champaign, IL, 1999.
78. Implementation of Campus-wide Wireless Network Services using ATM, Virtual LANs, and Wireless Basestations. by John W. Lockwood; IEEE Wireless Communications and Networking Conference (WCNC). September 21-23, 1999, New Orleans, LA. Paper TA3.3.
79. Multiclass Priority Fair Queuing for Hybrid Wired/Wireless Quality of Service Support by Jay Moorman and John W. Lockwood; IEEE Mobicom/WoWMoM. August 20, 1999, Seattle, WA, Pgs. 43-50.
80. ABR Architecture and Simulation for an Input-Buffered and Per-VC Queued ATM Switch, by Matthias Bossardt, Sueng-Yong park, John W. Lockwood, Sung-Mo Kang; IEEE Global Telecommunications Conference (GLOBECOM 1998), pp. 1817-1822. Sydney, Australia, Nov. 1998.
81. Providing Multicast Video on Demand using Native-mode Asynchronous Transfer Mode, by John W. Lockwood, S. M. Kang, A. Hossain, J. Hiltenbrant. IEEE International Symposium on Circuits and Systems (ISCAS'98), Monteray, CA, May, 1998.
82. Matrix Unit Cell Scheduler (MUCS) for Input-Buffered ATM Swithes by Haoran Duan, John W. Lockwood, Sung Mo Kang; IEEE Communications Letters. Volume 2, Number 1, January, 1998, pp. 20-23.
83. A High-performance OC-12/OC-48 Queue Design Prototype for Input-buffered ATM Switches, by Haoran Duan, John W. Lockwood, Sung Mo Kang, Jeff D. Will, IEEE Infocom '97, Kobe, Japan, April 7-11, 1997, pp 20-28.
84. Development of the iPOINT Testbed for Optoelectronic Asynchronous Transfer Mode Networking, by John W. Lockwood, S. M. Kang, S. G. Bishop, H. Duan, A. Hossain; International Conference on Information Infrastructure. April 25-28, 1996, Beijing, China. pp. 509-513.
85. An Efficient Input Queueing and Cell Scheduling Scheme for Scalable Ultra-Broadband Optoelectronic ATM Switching. by Haoran Duan, John W. Lockwood, Sung Mo Kang; Emerging High Speed Local-area Networks and Wide-area Networks: Photonics East Conference, SPIE'95, Volume 2608, Philadelphia, Pennsylvania. October, 1995, pp 107-108.
86. Scalable Optoelectronic ATM Networks: The iPOINT Fully Functional Testbed , by John W. Lockwood, Haoran Duan, James J. Morikuni, Sung Mo Kang, S. Akkineni, Roy H. Campbell; IEEE Journal of Lightwave Technology, June 1995, pp. 1093-1103.
87. FPGA Prototype Queueing Module For High Performance ATM Switching. by Haoran Duan, John W. Lockwood, Sung Mo Kang, Proceedings of the Seventh Annual IEEE International ASIC Conference. September, 1994, Rochester, New York. pp. 429-432.
88. The iPOINT Testbed for Optoelectronic ATM Networking, by John W. Lockwood, C. Cheong, Steve Ho, Ben Cox, Sung Mo Kang, Steve G. Bishop, Roy H. Campbell, Conference on Lasers and Electro-Optics (CLEO), May, 1993, Baltimore, Maryland, pp. 370-371.

Short Papers Published in Peer-reviewed, Refereed, and Archived Conference Proceedings

(In reverse chronological order - Most recent at the top)

1. NetFPGA - An Open Platform for Gigabit-rate Network Switching and Routing, by John W. Lockwood, Nick McKeown, Greg Watson, Glen Gibb, Paul Hartke, Jad Naous, Ramanan Raghuraman, and Jianying Luo IEEE International Conference on Microelectronic Systems Education (MSE'2007), June 3-4, 2007, San Diego, CA. [Presentation Slides]
2. Adaptive Control of FPGA Computation with Thermal Feedback; by Phillip H. Jones, Young H. Cho, John W. Lockwood; The Syndicated, Q4, 2006.
3. Implementation of Network Application Layer Parser for Multiple TCP/IP Flows in Reconfigurable Devices; by James Moscola, Young H. Cho, John W. Lockwood; 16th Annual Conference on Field Programmable Logic and Applications (FPL); Madrid, Spain, August 28-30, 2006; pp. 761-764.
4. Hierarchical Clustering using Reconfigurable Devices; by Shobana Padmanabhan, Moshe Looks, Dan Legorreta, Young H. Cho, and John W. Lockwood; Proceedings of 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM); Napa, CA, USA, April 24-26, 2006; pp. 327-328.
5. Tools for In-Circuit Testing of On-Line Content Processing Hardware, by Jeff Mitchell and John Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE), Anaheim, CA, June 2005.
6. Use of a Soft-Core Processor in a Hardware/Software Codesign Laboratory by Roger Chamberlain, John Lockwood, Saurabh Gayen, Richard Hough, and Phillip Jones; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE), Anaheim, CA, June 2005.
7. Microarchitecture Optimization for Embedded Systems, by David Schuehler, Benjamin Brodie, Roger Chamberlain, Ron Cytron, Scott Friedman, Jason Fritts, Phillip Jones, Praveen Krisnamurthy, John Lockwood, Shobana Padmanabhan, Huakai Zhang, Eighth Annual Workshop on High Performance Embedded Computing (HPEC), Massachusetts Institute of Technology Lincoln Laboratory, September 28-30, 2004.
8. Extracting and Improving Microarchitecture Performance on Reconfigurable Architectures, by Shobana Padmanabhan, Phillip Jones, David V. Schuehler, Scott J. Friedman, Praveen Krishnamurthy, Huakai Zhang, Roger Chamberlain, Ron K. Cytron, Jason Fritts, and John W. Lockwood; Workshop on Compilers and Tools for Constrained Embedded Systems (CTCES); Washington DC; Sept. 22, 2004
9. Implementation Results of Bloom Filters for String Matching, by Michael Attig, Sarang Dharmapurikar, and John Lockwood; In Proceedings of: IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 20-23, 2004. [Poster].
10. Secure Remote Control of Field-programmable Network Devices, Haoyu Song, Jing Lu, John Lockwood, James Moscola In Proceedings of: IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM), Napa, CA, April 20-23, 2004. [Poster].
11. Internet Worm and Virus Protection for Very High-Speed Networks, by John W. Lockwood, Seventh Annual Workshop on High Performance Embedded Computing (HPEC), Massachusetts Institute of Technology Lincoln Laboratory, September 23-25, 2003. [Presentation]
12. Internet-based Tool for System-on-Chip Integration, by David Lim, Christopher E. Neely, Christopher K. Zuver, John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'03), Anaheim, CA, June 2003
13. Internet-based Tool for System-On-Chip Project Testing and Grading, by Christopher E. Neely, Christopher K. Zuver, John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'03), Anaheim, CA, June 2003
14. Hot Interconnects 10 - Thinking beyond the Internet, Guest editor introduction, IEEE Micro, Volume 23, Issue 1, Jan. 2003, pp. 8-9
15. Platform and Methodology for Teaching Design of Hardware Modules in Internet Routers and Firewalls, by John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'2001), Las Vegas, NV, June 17-18, 2001, pp. 56-57.
16. Automated Team Project Management and Evaluation Through Interactive Web Modules, by John W. Lockwood, IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'99), Arlington, VA, July 19-21, 1999, pp. 26-27.
17. Distributed Learning via the World Wide Web Through Interactive Modules, by John W. Lockwood; IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'97), Arlington, VA, July 21-23, 1997, pp. 101-102.

1. "Network Packet Filtering" by John W. Lockwood, chapter in Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Edited by Scott Hauck and Andre DeHon, ISBN-13: 9780123705228, Elsevier, 2007.
2. "Information Processing at Very High-Speed Data Ingestion Rates" by J. Brian Sharkey, Doyle Weishar, John W. Lockwood, Ron Loui, Richard Rohwer, John Byrnes, Krishna Pattipati, David Cousins, Michael Nicolletti, Stephen Eick; Chapter 4 in Emergent Information Technologies and Enabling Policies for Counter Terrorism, Edited by Robert Popp and John Yin, ISBN-13: 9780471776154, IEEE Press/Wiley, 2006, Pages 75-104.
3. "Logic Synthesis for Field Programmable Gate Array (FPGA) Technology", by John W. Lockwood, chapter in The VLSI Handbook Edited by: W. K. Chen; ISBN-13: 9780849341991; New York: CRC Press LLC, 2006.

Workshops

1. Hands-on with the NetFPGA to build a Gigabit-rate Routers at Indian Institute of Science (IISc); Presented by John W. Lockwood, Jad Naous, and Kuruvilla Varghese; Bangalore, India, May 15-16, 2008.
2. Hands-on with the NetFPGA to build a Gigabit-rate Router at Beijing Jaiotong University; presented by John W. Lockwood, Jianying Luo, Kevin Xie, Walkie Que, and Defeng Li; Beijing, China, Apr. 23, 2008.
3. NetFPGA: Hands-on with the NetFPGA to build a Gigabit-rate Router; by John W. Lockwood, Gerald Adam Covington, Andrew Moore; Presented at EuroSys 2008; Glasgow, Scotland; Mar. 31, 2008
4. Hands-on with the NetFPGA to build a Gigabit-rate Router at NICTA; presented by John W. Lockwood, Glen Gibb, Jad Naous; Presented at the University of New South Wales (UNSW), Sydney, Australia, Feb. 6, 2008.
5. NetFPGA: Hands-on with the NetFPGA to build a Gigabit-rate Router; by Nick McKeown, John W. Lockwood, Jad Naous, Glen Gibb, Adam Covington; Presented at IEEE Hot Interconnects (HotI) - Symposium on High-Performance Interconnects; Stanford University, Stanford, CA; August 24, 2007
6. NetFPGA: An Open-source Hardware Platform for Networking Research and Teaching; by Nick McKeown, John W. Lockwood, Jad Naous, and Glen Gibb; Presented at ACM SigMetrics 2007: International Conference on Measurement and Modeling of Computer Systems; San Diego, CA; June 12, 2007
7. Liquid Architecture, by Phillip Jones, Shobana Padmanabhan, Daniel Rymarz, John Maschmeyer, David V. Schuehler, John W. Lockwood, and Ron K. Cytron; International Parallel and Distributed Processing Symposium: Workshop on Next Generation Software (NSF-NGS); Santa Fe, NM, April 26, 2004, Paper: W10-NSFNGS-13.
8. June 2002 FPX Workshop, John W Lockwood, Todd Sproull, James Moscola, David Schuehler, Dave Lim, Sarang Dharmapurikar, Chris Neely, Gigabit Kits Workshop, Saint Louis, MO, June 19-20, 2002.
9. January 2002 FPX Workshop, John W Lockwood, David Taylor, James Moscola, Todd Sproull, Dave Lim, Gigabit Kits Workshop, Saint Louis, MO, January 3-4, 2002.
10. August 2001 FPX Workshop, John W Lockwood, Henry Fu, Todd Sproull, Sarang Dharmapurikar, Edson Horta, Dave Lim Gigabit Kits Workshop, Saint Louis, MO, August 15-16, 2001.
11. January 2001 FPX Workshop John W Lockwood, David E. Taylor, Todd Sproull, Sarang Dharmapurikar, Florian Braun. Gigabit Kits Workshop, Saint Louis, MO, January 11-12, 2001.

Technical Reports and Thesis

1. A Collision Detection Chip on Reconfigurable Hardware, by Nuzhet Atay, John W. Lockwood, Burchan Bayazit; Washington University Dept. of Computer Science and Engineering; Technical Report WUCS-2005-033, 2005.
2. Design and Implementation of a String Matching System for Network Intrusion Detection using FPGA-based Bloom Filters, by Sarang Dharmapurikar, Michael Attig, John W. Lockwood, Washington University Dept. of Computer Science and Engineering : Technical Report WUCS-2004-012, 2004.
3. Multiflow TCP, UDP, IP, and ATM Traffic Generation Module, by Eliot I. Sinclair, John W. Lockwood, WUCSE-2003-24, April 24, 2003.
4. System-on-Chip Packet Processor for an Experimental Network Services Platform, by David Taylor, Alex Chandra, Yuhua Chen, Sarang Dharmapurikar, John Lockwood, Wenjing Tang, Jonathan Turner, WUCSE-2003-22, April 22, 2003.
5. Usage of the Statistics Counter Plus Component in Networking Hardware Modules, by Michael Attig, John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-25, August, 2002.
6. Implementation of a Pipelined Control Cell Processor , by Michael Attig and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-24, August, 2002.
7. Statistic Counter for Networking Hardware Modules, by Michael Attig and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-20, July, 2002.
8. Field Programmable Port Extender (FPX) User Guide: Version 2.2, by John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-02-15, June, 2002.
9. Packet Scheduling for Link-Sharing and Quality of Service Support in Wireless Local Area Networks, by Lars Wischhof and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-35, November, 2001.
10. Scalable IP Lookup for Programmable Routers, by David Taylor, John W. Lockwood, Todd Sproull, and David B. Parlour; Washington University, Department of Computer Science, Technical Report WUCS-01-33, October, 2001.
11. Synthesizable Design of a Multi-Module Memory Controller, by Sarang Dharmapurikar and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-26, October, 2001.
12. Implementation of an Open Multi-Service Router by Fred Kuhns, John Dehart, Ralph Keller, John Lockwood, P. Pappu, J. Parwatikar, Ed Spitznagel, Dave Richards, Dave Taylor, Jon Turner, and Ken Wong; Washington University, Department of Computer Science, Technical Report WUCS-01-20, August, 2001.
13. The FPX KCPSM Module: An Embedded, Reconfigurable Active Processing Module for the Field Programmable Port Extender (FPX), by Henry Fu and John W. Lockwood, Washington University, Department of Computer Science, Technical Report WUCS-01-14, July, 2001.
14. PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs), by Edson Horta and John W. Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-13, July, 2001.
15. Layered Protocol Wrappers for Internet Packet Processing in Reconfigurable Hardware, by Florian Braun, John W. Lockwood, Marcel Waldvogel; Washington University, Department of Computer Science, Technical Report WUCS-01-10, July, 2001.
16. OBIWAN - An Internet Protocol Router in Reconfigurable Hardware, by Florian Braun, Marcel Waldvogel, and John Lockwood; Washington University, Department of Computer Science, Technical Report WUCS-01-11, July, 2001.
17. "Hello World": A Simple application for the Field Programmable Port Extender (FPX), by John Lockwood and David Lim; Washington University, Department of Computer Science, Technical Report WUCS-00-12, July, 2000.
18. Parallel FPGA Programming over Backplane Chassis, by John Lockwood, Tom McLaughlin, Tom Chaney, Yuhua Chen, Fred Rosenberger, Alex Chandra, Jon Turner; Washington University, Technical Report WUCS-00-11, June 12, 2000.
19. Design and Implementation of a Multicast, Input-Buffered ATM Switch for the iPOINT Testbed, by John W. Lockwood; PhD Dissertation, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, 1995, UMI Number: 9625160.
20. The iPOINT Testbed for Optoelectronic ATM Networking, by John Lockwood, University of Illinois at Urbana-Champaign, Department of Electrical and Computer Engineering, Technical Report: UILU-ENG-93-0401. May, 1993.
21. SMAX: Simple Multicast ATM for XUNET, by John Lockwood, AT&T Bell Labs Technical Report, A Scalable, Modular Framework to support ATM Applications, Oct, 1994.
22. Proposed Mbone/Xunet Extensions, by John Lockwood, AT&T Bell Labs Technical Report, Oct, 1993.

Invited Talks

1. The NetFPGA: An open platform for full-rate data processing on Gigabit-speed networks, Invited talk by John W. Lockwood for: Centre for Electronics Design and Technology, India Institute of Science (IISc), Bangalore, India. May 13, 2008
2. The NetFPGA: An open platform for high-speed data processing and clean-slate network prototyping, Invited talk by John W. Lockwood for: Intel China Research Center, Beijing, China. Apr. 28, 2008.
3. Research and Teaching with the NetFPGA, Invited talk by John W. Lockwood for: Professor Workshop for the Xilinx University Program, Guilin, China. Apr. 26, 2008.
4. A Quick Update on High Speed Networking Systems, Invited talk by John W. Lockwodo for: Huawei, Beijing, China, Apr. 24, 2008.
5. NetFPGA: An open platform for high-speed data processing Invited talk by John W. Lockwood for: University of Glasgow, Glasgow, Scotland, Mar. 27, 2008
6. NetFPGA: An open platform for high-speed data processing, Invited talk by John W. Lockwood for: Agilent Laboratories South Queensferry, United Kingdom, Mar. 26, 2008
7. Prototyping Hardware-accelerated Routing on the NetFPGA, Invited talk by John W. Lockwood for: Juniper Networks, Sunnyvale, CA, Mar. 21, 2008
8. Rebuilding the Internet with Reconfigurable Hardware, Invited talk by John W. Lockwood for: University of California, Merced, California. Mar. 14, 2008
9. NetFPGA: An open platform for High-speed data processing & Network traffic filtering, Invited talk and demonstration by John W. Lockwood and Gerald Adam Covington at: Agilent Laboratories, Santa Clara, CA, Sep. 24 2008
10. NetFPGA: An Open Platform for Building Extensible Networks with Reconfigurable Hardware, Invited talk by John W. Lockwood for PRESTO, Princeton University, May 31, 2007.
11. Liquid Architecture - Results of Optimization of the LEON, Invited talk by John W. Lockwood for RAMP January 2007 Workshop, University of California, Berkeley, January 12, 2007.
12. Development of Next-generation Networks with Reconfigurable Hardware, Invited colloquia by John W. Lockwodo for: University of California, Riverside: Department of Computer Science and Engineering, April 3, 2006.
13. Measurement and Filtering of TCP/IP traffic flows at OC-48 Rates using Reconfigurable Hardware, Invited talk by John W. Lockwood at CAIDA of the University of California, San Diego, January 28, 2005.
14. Insecure Networks, Invited talk by John Lockwood for: Society of Women Engineers (SWE), St. Louis, MO, November 9, 2004.
15. Fast Content Processing in Reconfigurable Hardware Hardware, Invited talk by John Lockwood for: Crossbeam Systems, Boston, MA, September 13, 2004.
16. Intelligent Networks, Invited talk by John Lockwood and Jack Meier for: Technology Gateway : IT Meeting, St. Louis, MO, April 8, 2004.
17. Evaluation and Testing of Quality of Service in Realistic, High-Performance Networks, Invited talk by John Lockwood, Boeing - Quality of Service Summit, St. Louis, MO, February 16, 2004.
18. Application of Hardware Accelerated Extensible Network Nodes for Internet Worm and Virus Protection, Invited seminar talk by John Lockwood, Old Dominion University, Norfolk, VA, January 30, 2004.
19. Techniques to Achieve Multi-Gigabit/second Internet Worm and Virus Protectionwith Extensible Hardware, Invited talk, Extreme Networks, Santa Clara, CA, January 23, 2004.
20. Security for Internet Infrastructure, Invited panel talk by John Lockwood, TechConnect'03, St. Louis, MO, Oct. 2003
21. System-On-Chip Internet Firewall, Invited talk by John Lockwood, IEEE Computer Society International Conference on Microelectronic Systems Education (MSE'03), Anaheim, CA, June 2003
22. Extensible Networking in Reconfigurable Hardware, Invited Colloquium by John Lockwood, Georgia Tech, Center for Experimental Research in Computer Systems Colloquium: Atlanta, GA, February 20, 2003.
23. Extensible Networking Technology, Invited Talk by John Lockwood, Boeing, Advanced Networking Working Group Meeting, Saint Louis, MO, February 11, 2003.
24. Network Processing in Reconfigurable Hardware by John Lockwood, OpenSig 2002, Lexington KY, October 17-18, 2002.
25. Dynamically Reconfigurable Networking Hardware Platforms, by John W. Lockwood, NSF/Darpa Workshop on New Visions for Large-Scale Networks (LSN'01), Vienna, VA, March 12-14, 2001, Paper 63-LOC.
26. Rapid prototype of hardware-based networking modules on the Field-programmable Port Extender (FPX), by John W. Lockwood, NSF-PI Workshop on Networking, University of California, Irvine, November 1-3, 2000

1. Hands-on tutoral of the NetFPGA at ACM SigMetrics 2007: International Conference on Measurement and Modeling of Computer Systems, San Diego, CA, June 12, 2007.
   • Tutorial Presentation Slides
   • Photos from the Hands-on tutorial
2. Live demonstration of FPX hardware at the FCCM exhibition, by John W. Lockwood, Mike Attig, Haoyu Song, and Jing Lu; Napa, CA; Apr 21, 2004.
   • Photos from the demonstration event
   • Photos from the conference
3. Internet Worm and Virus Proteuction with Extensible Networks, Live demonstratations during annual review day at the Center for Security Technologies, by John W. Lockwood, Dave Schuehler, Mike Attig, and James Moscola, St. Louis, MO, Jan 26, 2004.
4. Internet Worm and Virus Protection in Dynamically Reconfigurable Hardware by John W. Lockwood, James Moscola, Matthew Kulig, David Reddick, Tim Brooks, at the Reagan Center for the Military and Aerospace Programmable Logic Device (MAPLD) Expo, Washington DC, 2003, Sep 9-11, 2003. [Photos]
5. Content-Scanning Module for an Internet Firewall, by James Moscola, John W. Lockwood, at FCCM Demo Night, Napa, CA, April 9, 2003. [Photos]
6. Control and Configuration Software for a Reconfigurable Networking Hardware Platform, by Todd Sproull and John W. Lockwood, at FCCM Demo Night, Napa, CA, April 24, 2002. [Photos]
7. Dynamic Hardware Plugins (DHPs) in an FPGA with Partial Run-time Reconfiguration (RTR), by Edson L. Horta and John W. Lockwood, at the Tenth ACM International Symposium on Field-Programmable Gate Arrays (FPGA'2002), Monterey, CA, February 24-26, 2002.

1. Success with Synplicity and the Reconfigurable Network Group, Identify Success Story, October, 2006.
2. Recognition Engines: New computer designs process networked "streams" of data for better spam and virus detection, Scientific American, January 2006.
3. 42nd Design Automation Conference Student Design Contest Winners Announced - Chip Design Magazine, June 8, 2005
4. Debugging of an Internet Packet Scheduler Using the Identify Software, by Christopher K. Zuver and John W. Lockwood, The Syndicated, Volume 4, Issue 4, 2004.
5. Blocking SPAM requires another can of worms, St. Louis Post-Dispatch, June 18, 2004.
6. Global Velocity Inc., Midwest Technology Journal, May 2004.
7. Global Velocity closes on $1.5 Million Round, Silicon Valley biz ink (PR Newswire), April 27, 2004.
8. Device guards Net against viruses, Technology Research News, December 17, 2003
9. System halts computer viruses, worms, before end-user stage, Washington University Record, Nov. 5, 2003
10. Extensible Network Security Device Built with the Amplify Solution, by John W. Lockwood, The Syndicated, Volume 3, Issue 3, 2003.
11. CSE beats odds, receives three NSF 2003 Information Technology Research grants, in WU Engineering News, Fall 2003, p. 7.
12. Washington University in St. Louis ranks 9th for National Universities with Doctoral programs, according to US News and World Reports 2004 rankings
13. Washington U. professor offers a Sobig answer, Saint Louis Post-Dispatch, Front page, Sunday business section, August 24, 2003
14. One Hour Repair - Hardware adds features must faster, Washington University Record, Vol. 27, Number 7, October 11, 2002.
15. Hot Interconnect wrestles with wire-speed challenges, CommsDesign, August 23, 2002.
16. FPGA Platform Fuels Study of Reconfigurable Networks, EE Times, Issue 1228, July 22, 2002.

Education

• University of Illinois
  Department of Electrical and Computer Engineering
  • PhD: Aug 1993-Oct 1995
    • Thesis: Design and Implementation of a Multicast, Input-Buffered ATM Switch for the iPOINT Testbed:
      Presents the design of a novel input-buffered switch and details of the implemention using all Field Programmable Gate Array (FPGA) logic.
    • GPA: 5.0/5.0
  • MS: Aug 1991-May 1993
    • Thesis: The iPOINT Testbed for Optoelectronic ATM Networking
    • GPA: 5.0/5.0
  • BS: Aug 1987-May 1991
    • GPA: 4.7/5.0 (Technical: 4.9/5.0)
    • Honors & Dean's list

  • Classwork
    • Computer Networking
    • Computer Architecture
    • Parallel Systems and Algorithms
    • Circuits and VLSI Design
    • Optics & Semiconductors

Technical Skills

• Reprogrammable Logic: Designed, synthesized, tested, and implemented Field Programmable Gate Array designs in: Xilinx (Virtex, XC4000-series, XC3000-series) and Altera (Max and Flex) technologies.
• Hardware Synthesis: VHDL Simulation and Synthesis with Synplicity, Synopsys, ViewLogic, and Mentor Graphics tools
• Data Networking: Configuration of Cisco routers (IOS), Fore switches, and Xylan Omniswitch systems to implement campus LANs and WANs.
• Programming: C++, C, Perl, Pascal, Assembly
• Web/CGI/Database
  • Developer, owner, programmer & operator of Gradebot.com
    • Designed and Implemented WebBasket electronic commerce tool.
    • Designed and Implemented Distributed Learning tools for automated grading of on-line homeworks and management of class projects and grades.
    • Manage conference submissions and review process
  • Developed components of NetDocs (an Interactive, web-based tools for Network Mangement) for the NCSA : Network Development Group :
• Operating Systems : Self-administrator for LINUX server and Windows desktop systems.

Professional Service, Honors, and Awards

• Professional Society Leadership
  • General Chair, Hot Interconnects 16 Symposium on High Performance Interconnects (2008)
  • Steering Committee, HotI Symposium on High Performance Interconnects (2004, 2005, 2006, 2007, 2008)
  • Steering Committee, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2008)
  • General Co-Chair, Hot Interconnects 15 Symposium on High Performance Interconnects (2007)
  • Symposium Chair, Advances for Networks & Internet, IEEE GlobeCom, November 2005.
  • General Chair, MSE '05: International Conference on Microelectronic Systems Education (2005)
  • Panel Co-Chair, Field-Programmable Gate Arrays Conference (2005): FPGA Startups: Diamonds or Dust
  • General Chair, Hot Interconnects 11 Symposium on High Performance Interconnects (2003)
  • Program Chair, MSE '03: International Conference on Microelectronic Systems Education (2003)
  • Guest Editor, IEEE Micro: (Jan 2002, Jan 2003)
  • Program Chair, Hot Interconnects 10 Symposium on High Performance Interconnects (2002)
  • Program Co-Chair, Hot Interconnects 9: Symposium on High Performance Interconnects (2001)
  • Proceedings/Web Chair, MSE '01: International Conference on Microelectronic Systems Education (2001)

• Professional Society Service
  • Program Committee, ACM SIGCOMM (2008)
  • Program Committee, Symposium on Architectures for Networking and Communications Systems(ANCS) (2008)
  • Program Committee, Field-Programmable Gate Arrays (FPGA) (2004, 2005, 2006,2007,2008)
  • Program Committee, IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM) (2007, 2008)
  • Program Committee, International Conference on Field Programmable Logic and Applications (FPL) (2005, 2006, 2007)
  • Session Chair, International Conference on Field Programmable Logic and Applications (FPL) (2006)
  • Session Chair, Hot Interconnects 14 Symposium on High Performance Interconnects (2006)
  • Technical Program Committee, Intl. Working Conference on Active Networks (IWAN) (2002, 2003, 2004, 2005)
  • Session Chair, Field-Programmable Gate Arrays (FPGA) (2004)
  • Technical Program Committee, Symposium on High Performance Interconnects (Hot Interconnects) (2002, 2003, 2004, 2005)
  • Reviewer: IEEE Transactions on Education (2007)
  • Reviewer: IEEE Transactions on Networking (2004)
  • Reviewer: IEEE Transactions on Computers (2004)
  • Reviewer: Journal of Systems and Software (2003)
  • Reviewer: IEEE Transactions on Mobile Computing (TMC) (2003)
  • Reviewer: Cluster Computing Journal (2003)
  • Reviewer: The Computer Journal (2003)
  • Reviewer: International Conference on Field Programmable Logic and Applications (FPL) (2003)
  • Judge, Design Automation Conference (DAC): SIGDA PhD Forum & Student Design Contest (2003, 2004, 2005, 2006, 2007)
  • Reviewer, ACM Transactions on Embedded Systems (TECS) (2002, 2003)
  • Reviewer, Workshop on Network Processors - NP2 (2002)
  • Reviewer, IEEE Journal on Selected Areas of Communication (JSAC) (2002)
  • Reviewer, IEEE Transactions on Very Large Scale Integration Systems (TVLSI) (2001)
  • Reviewer, Computer Networks Journal (2001)
  • Reviewer, ACM Sigmetrics (2001)
  • Reviewer, Globecom (2001)

• Professional Society Membership
  • Association for Computing Machinary (ACM)
    • SIGDA: Design Automation
    • SIGCOMM: Data Communication
  • Institute of Electrical and Electronics Engineers (IEEE)
    • IEEE Computer Society
    • IEEE Communications Society
  • International Game Developers Association (IGDA)
  • Tau Beta Pi (Engineering Honor Society)
  • Eta Kappa Nu : (Electrical Engineering Honor Society)