Project Motivation

• Project Motivation

  In the past, there has been a hard line between software and hardware systems. Software-based systems were highly reprogrammable while hardware systems provided optimal performance. By implementing systems with Dynamic Hardware Plugins (DHPs), it is possible to possible to combine the advantages of both.
  

• The FPX Solution

  The Field-programmable Port Extender (FPX) is an open platform that augments a network with reprogrammable hardware. It enables new data-processing hardware to be rapidly developed, prototyped, and deployed over the Internet. A diagram of the FPX combined with the Washington University Gigabit Switch (WUGS) is shown above. This enhanced system enables research, development, and implementation of new hardware-based networking applications, intelligent packet processing, custom data processing, and real-time systems.

• Project Status

  Thus far, eighty five copies of the FPX platform have been fabricated. It has been used to: route Internet packets; compress, encrypt, and buffer data; transcode motion JPEG images; and process multiple flows of video. By using FPGA hardware, rather than a microprocessor, the packet processor can perform full processing of packet payloads at Gigabit rates.

• Latest Technology

  To see the most recent advances from the group that developed the FPX,
  see the Reconfigurable Hardware Group homepage.

Publications and References

• FPX Publications
  • Journal and Conference Papers
  • Workshops
  • Technical Reports
  • Related Web Pages
  • BiBTeX Listing

• The FPX Platform
  • The FPX is an open Hardware platform designed and implemented at Washington University in Saint Louis that can be used to implement OC-48 speed packet processing functions in reconfigurable hardware. The FPX provides a mechanism for networking hardware modules to be dynamically loaded into a running system. The platform allows networking routers to evolve over time to provide additional features.

• Multi-Service Switching and Routing
  The FPX is used with the Washington University Gigabit Switch (WUGS) to implement a high-speed Multi-Service Router (MSR) that provides a system that is robust to extreme network conditions.

• Fast Internet Route Lookup
  • An efficient, scalable lookup engine has been designed to achieve high-performance Internet routing using a small portion of FPGA logic and commodity random access memory. Based on the Eatherton Tree Bitmap Algorithm, the Fast IP Lookup (FIPL) engine can be scaled to achieve over 9 million Internet route lookups per second. The attributes of the system make it ideal for System-On-Chip (SoC) packet processing platforms, including the FPX.

• Layered Protocol Wrappers
  • The Wrapper Library is a collection of VHDL components that process high-level Internet protocols directly in hardware. The hardware library has four components that are used together to transmit and receive: fixed-length cells, variable-length Adapation-Layer 5 (AAL5) frames, Internet Protocol (IP) packets, and User Datagram Procotol (UDP) frames. All header checksums and lengths fields are checked and/or computed within the wrapper library components.

• NCHARGE: FPX Control Software
  • A suite of tools called NCHARGE (Networked Configurable Hardware Administrator for Reconfiguration and Governing via End-systems) has been developed to simplify the co-design of hardware and software components within an FPGA-based Internet router or firewall. NCHARGE provides a standard Application Programming Interface (API) between software and reprogrammable hardware modules. Using this API, multiple software processes can communicate to one or more hardware modules using standard TCP/IP sockets. NCHARGE also provides a Web-Based User Interface to simplify the configuration and control of an entire network switch that contains several software and hardware modules.

• PARBIT: Partial Bitfile Reconfiguration
  • PARBIT transforms FPGA configuration bitfiles, called bitstreams, to enable Dynamically Hardware Plugins modules for the RAD FPGA on the Field-programmable Port Extender (FPX).

• KCPSM: Embedded Soft-core Processor Module
  • The FPX KCPSM Module is a small, active, and reconfigurable processing node for the Field-programmable Port Extender (FPX) using the Layered Protocol Wrappers and the KCPSM. It allows the program memory of the KCPSM to be dynamically reprogrammed over the network through the use of UDP Datagrams; therefore, the function of the processing node can be changed dynamically on a packet by packet basis. It is primarily designed for the FPX, but it can be changed to use in any FPGA-based design.

• FPX Video Recoder
  • A hardware-based JPEG recoding module has been developed for the FPX. This module allows the bandwidth of data for a motion JPEG video stream to be adjusted midway through the network by dropping high-order coefficients of the video image data.

• FPX Multi-Video Processing Platform (MVP₂)
  • In order to support image gathering from multiple cameras, a system is being developed that supports multiple cameras and display devices. Video is captured from one or more sources and processed by a Video Input Module (VIM). Data is stored in a Network Packet Frame Buffer (NPFB). Lastly, the Video Rendering Engine generates output images.

• SDRAM Controller: memory Controller with Performance Optimization
  • The SDRAM controller is the interface between the user modules on the Field-programmable Port Extender (FPX) and the off chip SDRAM on the FPX. Multiple modules contend for the SDRAM access and the SDRAM controller arbitrates between the requests made by each module and provides access to the SDRAM.

• Testbench Generator
  • The simulation of networking hardware is complex due to the need to handle multiple flows of different traffic types. An testbench generator is being constructed that allows multiple flows to be constructed automatically.

• Statistics Module
  • In order to track the operation of networking hardware circuits, a statistics module is being developed that tracks events and allows counts to be read over the network

Research Opportunities

• Graduate Research Courses for WashU Students
  • Full Courses
    • E71 CS 535m: Acceleration of Networking Algorithms in Reconfigurable Hardware, Fall 2003
    • E71 CS 536m: Reconfigurable System on Chip Design, Fall 2002
    • E71 CS 535m: Acceleration of Networking Algorithms in Reconfigurable Hardware. Fall 2001
  • Seminar Courses
    • E71: CS 6814 : Research Seminar on Reconfigurable Hardware, Fall 2003
    • E71: CS 6813 : Research Seminar on Reconfigurable Hardware, Spring 2003
    • E71: CS 6812 : Research Seminar on Reconfigurable Hardware, Fall 2002
    • E71: CS 6811 : Research Seminar on Reconfigurable Hardware, Spring 2002
  • Article about Courses
    • John W. Lockwood, Platform and Methodology for Teaching Design of Hardware Modules in Internet Routers and Firewalls, MSE, 2001