Final Project

Network Traffic Generator

Updated 12/12/01

John Cummings

Jeyashankher Ramamirtham

Abstract

We implemented a network traffic generator capable of generating six different patterns of cells. On a pre-determined VCI, the generator accepts a control cell that is used to specific the pattern of cells to be generated and several variables used in generation. The current implementation currently accepts a maximum clock of 38 MHz, which can be improved by pipelining calculations in the design. In actual hardware tests, the generator performed as specified with no problems.

Introduction

The purpose of this project is to implement a network traffic generator on the FPX that is able to send ATM cells over a link with various probabilistic patterns determined by control cells. The generator has two specific applications:

1. Research - The generator will allow researchers to study various patterns of data and their effects on new networking devices.

2. Industry - The generator can be used by engineers to perform testing on a networking device, such as a router, to ensure it is ready to be marketed.

Overview

Figure 1 shows that the generator is divided into two parts: the control cell processor (CCP) and the network traffic generator (NTG). The CPP is responsible for extracting fields from the control cell and informing the NTG that a new command is ready to be processed. The NTG is responsible for generating cells using the parameters it receives from the CCP.

Figure 1 - Block diagram of the Network Traffic Generator

The opcodes are shown in table 1 and the traffic patterns associated with them are shown in figure 2. Each square represents one cell.

Table 1 - Input opcodes

Input Opcode (hex)	Traffic Pattern
00	None. Generator is idle.
02	Constant interarrival time (IAT) cells
04	Variable IAT cells
06	Constant IAT, constant burst length (BL)
08	Variable IAT, constant BL
0A	Constant IAT, variable BL
0C	Variable IAT, variable BL

Figure 2 - Traffic patterns

Figure 3 shows the control cell format used in this project. When the control cell has been processed by the generator, the OpCode is incremented and the entire cell is passed out of the generator before any traffic is generated. The output control cell is used to verify that the command was received.

Figure 3 - Control Cell

The module file for NCHARGE is shown in listing 1.

Listing 1 - Module file for NCHARGE

The Control Cell Processor (CCP)

Figure 4 shows the block diagram of the CCP, and figure 5 shows the finite state machine (FSM). A cell enters the CCP at D_Mod_In, and after 14 clock cycles, the entire cell is buffered in the registers. The CountTo14 block raises the Done signal when it has counted to 14, which started when the SOC_Mod_In signal went high. The Done signal alerts the FSM that the cell is ready to be processed. If the cell is a control cell (VCI=23h), then the FSM will inactivate the enable signals of registers (causing the data to stop shifting) and activate the NewCommand signal to inform the NTG that a new command is ready to be processed. When the NTG activates the NewCommandAck to inform the CPP that it is ready to receive the command, the FSM enables the registers to shift the data out of the CCP.

Figure 4 - Control Cell Processor block diagram

Figure 5 - Control Cell Process FSM

It is important to note that while the CCP is waiting for the NewCommandAck signal, any other cells that attempt to enter the FPX will be dropped. Therefore, back-to-back control cells will not be processed and should be spaced out enough to give the NTG time to acknowledge the first control cell.

If the cell in the registers is not a control cell, the FSM will hold the enable signals high, causing the cell to shift out of the CCP. If the NTG is disabled, this data will be forwarded out of the NTG. If the NTG is active, this data will be dropped.

The Network Traffic Generator (NTG)

Figure 6 shows the block diagram of the NTG. Using the fields extracted from the control cell, an inter-arrival time (IAT) random number and burst length (BL) random number are generated by the random number generators (RNG). The IAT Timer and BL Timer are set by the RNGs and are used by the Cell Generator to determine how long to wait between cells and how many cells to send in one burst. The SOC_Out_Mod signal is generated with each outgoing cell.

Figure 6 - Network Traffic Generator block diagram

The RNGs are implemented using linear feedback shift registers (LFSR). Figure 7 shows the block diagram of an 32-bit LFSR, and figure 8 shows the block diagram of a 4-bit LFSR. Bits in the register are tapped and XORed together. The result is a new bit to be shifted into the most significant place of the register. These registers generate uniformly distributed random numbers. The location of the taps were selected based on [Alfke].

Figure 7 - 32-bit Linear Feedback Shift Register (LFSR)

Figure 8 - 4-bit LFSR for burst length

Figure 9 shows the pass-through hardware that allows the NTG to forward control cells to the output before generating any traffic.

Figure 9 - Pass-through hardware in the NTG

Synthesis

The results of the place-and-route are shown in listing 2.

Listing 2 - Results of place-and-route

The timing results are shown in listing 3.

Listing 3 - Timing results

Testing

Testing occurred in two stages. Stage 1 testing was performed with ModelSim and involved the simulation of all part of the implementation. Stage 2 testing was performed on the actual hardware. In simulation, the generator performed to specification with no problems. In hardware, the generator performed as expected. It successful returned an output control cell and generated the requested traffic.

Conclusions

The network traffic generator was fully implemented. Future work on the device will include pipelining the calculations to allow the generator to perform at 100 MHz. The current speed is 38 MHz, which does not meet our goal. Nevertheless, all traffic pattern are generated as expected. The generator is ready to be used by researchers and test engineers to study the effects of network traffic on other networking devices.

References

Alfke, Peter. "Efficient Shift Registers, LFSR Counters, and Long Pseudo-Random Sequence Generators." http://www.xilinx.com/xapp/xapp052.pdf

George, Maria and Peter Alfke. "Linear Feedback Shift Registers in Vertex devices." http://www.xilinx.com/xapp/xapp210.pdf