----------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used     --
-- solely for design, simulation, implementation and creation of    --
-- design files limited to Xilinx devices or technologies. Use      --
-- with non-Xilinx devices or technologies is expressly prohibited  --
-- and immediately terminates your license.                         --
--                                                                  --
-- Xilinx products are not intended for use in life support         --
-- appliances, devices, or systems. Use in such applications are    --
-- expressly prohibited.                                            --
--                                                                  --
-- Copyright (C) 2001, Xilinx, Inc.  All Rights Reserved.           --
----------------------------------------------------------------------

-- You must compile the wrapper file cntr_ram.vhd when simulating
-- the core, cntr_ram. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "Coregen Users Guide".

-- The synopsys directives "translate_off/translate_on" specified
-- below are supported by XST, FPGA Express, Exemplar and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).

-- synopsys translate_off
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

Library XilinxCoreLib;
ENTITY cntr_ram IS
	port (
	addra: IN std_logic_VECTOR(7 downto 0);
	addrb: IN std_logic_VECTOR(7 downto 0);
	clka: IN std_logic;
	clkb: IN std_logic;
	dinb: IN std_logic_VECTOR(15 downto 0);
	douta: OUT std_logic_VECTOR(15 downto 0);
	ena: IN std_logic;
	enb: IN std_logic;
	web: IN std_logic);
END cntr_ram;

ARCHITECTURE cntr_ram_a OF cntr_ram IS

component wrapped_cntr_ram
	port (
	addra: IN std_logic_VECTOR(7 downto 0);
	addrb: IN std_logic_VECTOR(7 downto 0);
	clka: IN std_logic;
	clkb: IN std_logic;
	dinb: IN std_logic_VECTOR(15 downto 0);
	douta: OUT std_logic_VECTOR(15 downto 0);
	ena: IN std_logic;
	enb: IN std_logic;
	web: IN std_logic);
end component;

-- Configuration specification 
	for all : wrapped_cntr_ram use entity XilinxCoreLib.blkmemdp_v4_0(behavioral)
		generic map(
			c_ysinitb_is_high => 1,
			c_yweb_is_high => 1,
			c_has_enb => 1,
			c_has_ena => 1,
			c_write_modeb => 0,
			c_pipe_stages_b => 0,
			c_write_modea => 0,
			c_pipe_stages_a => 0,
			c_yenb_is_high => 1,
			c_addrb_width => 8,
			c_has_dinb => 1,
			c_has_dina => 0,
			c_has_doutb => 0,
			c_has_douta => 1,
			c_ymake_bmm => 0,
			c_ysinita_is_high => 1,
			c_reg_inputsb => 0,
			c_has_rfdb => 0,
			c_reg_inputsa => 0,
			c_has_rfda => 0,
			c_yprimitive_type => "256x16",
			c_yhierarchy => "cntr_ram",
			c_mem_init_file => "mif_file_16_1",
			c_yclka_is_rising => 1,
			c_sinita_value => "0",
			c_has_sinitb => 0,
			c_has_sinita => 0,
			c_depth_b => 256,
			c_depth_a => 256,
			c_has_ndb => 0,
			c_has_nda => 0,
			c_has_web => 1,
			c_sinitb_value => "0",
			c_yuse_single_primitive => 1,
			c_has_wea => 0,
			c_default_data => "0",
			c_has_default_data => 1,
			c_ywea_is_high => 1,
			c_yclkb_is_rising => 1,
			c_width_b => 16,
			c_width_a => 16,
			c_ytop_addr => "1024",
			c_yena_is_high => 1,
			c_limit_data_pitch => 18,
			c_ybottom_addr => "0",
			c_has_rdyb => 0,
			c_has_rdya => 0,
			c_has_limit_data_pitch => 0,
			c_enable_rlocs => 0,
			c_addra_width => 8);
BEGIN

U0 : wrapped_cntr_ram
		port map (
			addra => addra,
			addrb => addrb,
			clka => clka,
			clkb => clkb,
			dinb => dinb,
			douta => douta,
			ena => ena,
			enb => enb,
			web => web);
END cntr_ram_a;

-- synopsys translate_on