## Makefile for compiling and simulating the statistics module

# created August 13th, 2003
# Author: Michael Attig (mea1@arl.wustl.edu)

WORK = work
VCOM = vcom -93 -work $(WORK)
VSIM = vsim
VHDL_DIR = ../vhdl

targets:: 
	@echo "targets are:"
	@echo "  compile  --- compile your vhdl files
	@echo "  sim      --- simulate your top level file

compile::
	if [ ! -d $(WORK) ] ; then vlib $(WORK) ; fi

	$(VCOM) $(VHDL_DIR)/cntr_ram.vhd

############

#  	Enter any other files you need to compile here
# 	Note they must be ordered from the bottom of your hierarchy
# 	to the top of it (Hence, stat_mod is the last file listed, as
# 	it should be at the top of your hierarchy.

###########

	$(VCOM) $(VHDL_DIR)/stat_mod.vhd


sim:: 
	$(VSIM) -lib $(WORK) stat_mod test.do