LIBRARY IEEE ;
USE IEEE.STD_LOGIC_1164.ALL ;
USE IEEE.STD_LOGIC_ARITH.ALL ;

ENTITY stat_mod IS

  PORT(clk              : IN STD_LOGIC ;
       reset_l          : IN STD_LOGIC ;
       inc_event_1      : IN STD_LOGIC ;
       cntr_read        : IN STD_LOGIC ;
       event_1_num      : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;

       data_strobe      : OUT STD_LOGIC ;
       cntr_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
       cntr_ready       : OUT STD_LOGIC 
       );

END stat_mod;

ARCHITECTURE structure OF stat_mod IS
  
-------------------------------------------------------------------------------
-- Note: The following two lines are used in the synthesis step when we build
-- this component.  They specifiy to the program to look for extrnal files for
-- a description of the component.  
-------------------------------------------------------------------------------
  
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------

  COMPONENT cntr_ram
    PORT (
      clka              : IN STD_LOGIC ;
      clkb              : IN STD_LOGIC ;
      addra             : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
      addrb             : IN STD_LOGIC_VECTOR(7 DOWNTO 0) ;
      dinb              : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;
      web               : IN STD_LOGIC ;
      ena               : IN STD_LOGIC ;
      enb               : IN STD_LOGIC ;
      douta             : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
      );
  END COMPONENT ;

-------------------------------------------------------------------------------
-- Signal Declarations
-------------------------------------------------------------------------------



  
-- Synplicity black box declaration
attribute syn_black_box : boolean;
attribute syn_black_box of cntr_ram: component is true;
  
-- Beginning of architecture
BEGIN


-- Put processes, logic, and assignments here.
  

-------------------------------------------------------------------------------
-- Port Maps
-------------------------------------------------------------------------------

-- Instantiate cntr_rams here


END structure ;