Machine Problem 3

Bloom Filter Analyzer

Introduction

SRAM Timing & Interface

In this MP we will implement an analyzer to remove reporting false positives.  Thus we will need to add functionality to the options processor.  This entails using SRAM.  You will be provided with a SRAM interface circuit.  This interface allows two different modules to share SRAM.  However, we have only one module, so the second interface will be unused.  The signals of interest are enumerated below.  Note that the snort_app entity has changed from previous machine problems.  You will need to adhere to this structure for MP3 to work properly.  The entity declaration has been provided for you in the distribution file. 

• mod1_req - signal to request use of SRAM
• mod1_gr - signal to communicate you are permitted to access SRAM
• mod1_rw - read/write signal, read operation when '1', write operation when '0'
• mod1_addr - 19 bit address to use
• mod1_d_in - data returning from SRAM (IN to your analyzer)
• mod1_d_out - data to be sent to SRAM (OUT of your analyzer)

A sample timing diagram is shown below in Figure 1.  As can be seen, you can perform reads and writes in the same request instance.  This is thanks to the ZBT (zero-bus turnaround) SRAM that we use.  Note that the read delay is 4 clock cycles.  While the timing diagram of Figure 1 shows mod1_gr being asserted the clock cycle after mod1_req, this is not necessarily the case.

Figure 1: SRAM Timing.

As shown in the Figure, you must hold mod1_req asserted until your memory transactions are complete.  When grant is de-asserted, you must de-assert request as soon as possible.  Once you have been granted access to SRAM, you retain access until you de-assert request. 

References

• SRAM Interface Timing / Signal Descriptions

Directions:

• Part 0: Download the distribution file for MP3.  This will be what your circuit communicates with to perform memory transactions.

  • Please note that the testbench has been modified from previous machine problems.

• Part 1: Creating an analyzer

  • You analyzer will need to be able to add strings to SRAM. 
  • The calculation of the address to place it at is based on the string itself.  We will compute a hash function, similar to MP2 in order to accomplish this.
  • However, the random value seed will be different (it can be found in the analyzer_values.vhd file). 
  • Note that by using the analyzer values, you will compute a 17 bit address.  The reason for this is that we will do "burst" reads to SRAM when we do an access.  A 10-byte string requires 3 36-bit words to store.  We'll simplify address calculation by leaving space for 4 words (could store 18 byte strings).  When doing this "burst" read, however, note that you have to increment the lower two bits of the address you are putting out in order to read the correct location.  (Remember, the SRAM address is 19 bits.)  As a further simplification, just use bits 31 downto 0 in an SRAM entry.  In this way, you don't have to worry about byte alignment.
  • For the purposes of this assignment, if when adding a string there is already a string there, you may overwrite it.  (i.e. don't worry about hash collisions)
  • Operation with the bloom filter
    • When the bloom filter detects a potential match, instead of creating an alert message, we'll need to redirect what could have matched to be input to the analyzer.
    • The analyzer will compute the hash over the potential offending string.
    • It will then check SRAM to see if this string is stored at that location.
    • If so, we have a definite match, and this string must be reported. 
  • While the analyzer is querying SRAM, the pipeline needs to be paused.  A pause signal was already provided in MP2 to allow this.  However, it was always de-asserted (set to '0').  You will need to modify this signal to appropriately pause the circuit when doing SRAM queries or adding strings to SRAM.  You will probably have to back up the pipeline also. 
  • Make your analyzer operate as quickly as possible (< 20 cycles).

• Part 2: Change the CPP

  • We will add a new opcode for this MP. 
  • Opcode x70.will be for adding a string to SRAM.
  • The format shown in Figure 2.

    

    Figure 2: Control packet format for Opcode x70.

  • You will need to count this new opcode as well.

• Part 3: Wire it together

  • Modify the CPP entity in order to handle this new opcode
  • Modify the option processor entity in order to accept new control signals and strings that are to be added.
  • Change the offending_signature is in the options processor to be the queried string if it is found in SRAM.

• Part 4: Simulation

  •  Rather than provide test cases for you, you will have to prove to us that your circuit is working.
  •  Nothing fancy is required here.  Just show a couple of strings being programmed in the bloom filter and analyzer and that the string will be detected. 

• Part 5: Synthesis and Build

  • Use Synplicity to make an edn file for your design.  Follow the steps given in MP1.

  • Once you have completed synthesis, use the provided makefile in the backend directory.  From a cygwin shell, type 'make build'.
  • If you want to change the target frequency, you can change all 4 values in the network_application_core.ncf file.  Currently, the rad_clk period is set to 13.333 ns (75 MHz).
  • This will generate a bitfile if there are no errors. You will submit this bitfile to the online test server to test it in hardware.

Things to Turn In:

Here is a checklist of the things you need to turn in:

• Part 1: All vhdl code written. ( 9 pts)

• Part 2: All modified code. ( 2 pts)

• Part 3: All modified code. ( 2 pts)

• Part 4: Synthesis and Build

  • Also submit the network_application_core.par file generated after running the build scripts.  ( 2 pts)

  • A simple simulation that proves that these new opcodes work.  ( 10 pts)

  • Submit the requested waveforms and vhdl to the Electronic Homework Server. ( 25 pts)

  • Submit synthesized .bit file to the test server where it will be tested in hardware. ( 75 pts)

    • Click on the Test Bitfile link on the left
    • To log in use the User Name: cse535
    • Password: soc_snort

  • Follow the instructions on the server, it will inform you if your design passed or not