PARBIT: PARtial BItfile Transformer

 V2.00 New Feature: IP (Intellectual Property) Mode

Introduction

PARBIT is a tool that transforms FPGA configuration bitfiles, called bitstreams, to enable Dynamically Hardware Plugins modules in the Field-programmable Port Extender (FPX).  The tool accepts options to generate a bitstream, which can load a DHP module into any region of the Reprogrammable Application Device (RAD) on the FPX. It also can be used to implement partial run-time reconfiguration (P-RTR) with VIRTEX Xilinx FPGAs.

Documentation

• IP Mode Paper: Edson L. Horta, John W. Lockwood, Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs,14th International Conference on Field Programmable Logic and Applications (FPL), Springer LNCS 3203, Antwerp, Belgium, August 2004, pp. 975-979.
• Summary Paper: Edson L. Horta, John W. Lockwood, David E. Taylor, David Parlour, Dynamic Hardware Plugins in an FPGA with Partial Run-time Reconfiguration. Design Automation Conference (DAC), New Orleans, LA, June 10-14, 2002.
• Detailed Report: PARBIT: A Tool to Transform Bitfiles to Implement Partial Reconfiguration of Field Programmable Gate Arrays (FPGAs), by Edson Horta and John W. Lockwood, Washington University, Department of Computer Science, Technical Report WUCS-01-13, July, 2001.

Requirements

It is possible to run PARBIT under Windows and Unix. In order to run under Windows, one must have installed the GNU Tool Environment called Cygwin (www.Cygwin.com). To run PARBIT under Unix, it is necessary only the executable file (parbit).

Design Flow

The design flow consists on generating the bitstream files from Xilinx CAD tools and run PARBIT with these files, to generate the partial bitstream.

There are three operation modes defined by the user parameters:

• Slice: in this mode the user specifies a slice containing one or more full CLB columns. The tool generates the partial bitstream with these columns, in the same position they were in the original bitstream file.
• Block: in this mode it is possible to define an area inside the CLB columns of the chip, without the top and bottom IOB frame control bits. Then, the user defines where to put this block, in a bitstream of the same type as the original one (target bitstream)
• IP (Intellectual Property): this mode is similar to the previous one, except that the Target FPGA must be different from the original bitstream. It is possible to generate a reconfigurable module (IP) in an FPGA and download it into a larger one.

  The following files are used by PARBIT, to generate the partial bitfile:

• Original - Bitstream file generated by Xilinx tools. This file contains the reconfigurable area that is extracted by PARBIT and transformed in a partial bitstream file. In the Slice Mode the reconfigurable area is placed in the same location it was set in the original design. In the Block Mode this area is the same, but it is placed in a different location.

• Target - Bitstream file generated by Xilinx tools. It is necessary only in Block Mode. This file contains the fixed configuration for the FPGA, plus an empty area reserved to receive the reconfigurable area generated by PARBIT. The location of this empty area has to be passed to the tool (TargetRow, TargetColumn) and must have the same size as the partial reconfigurable area, defined in the option file.
• Option - Text file containing user options. Each line of this file has the following format: OPTION:VALUE

The tool generates the partial bitstream file containing the area selected by the user (from the original bitstream) and this file will be used to reconfigure the target device.  

Download

The following files are available:

• parbit.exe (36 Kbytes)- Windows (Cygwin) executable file;
• parbit.1 (8 Kbytes) -  reference manual file (NROFF Format);
• parbit-expl.tar (200 Kbytes)- Example Files for Windows (Cygwin), with executable, option, target and original file (XCV50E). Uncompress the file and type "parbit parbit-gask.opt gask_dhp.bit gask-part.bit gask_inf.bit " to generate the partial bitstream file;
• gask-design.tar (70 Kbytes) -files utilized to generate the bitstreams for the example in the previous item;
• FPX-license.txt ( 3 Kbytes) License distribution file;

Limitations

The current limitations of PARBIT (V2.00) are:

• Accepts only Virtex-E devices;
• Generates configuration bits for CLB columns only;
• Target Row must be 1 for IP Mode.

Disclaimer

• Only non-commercial, not-for-profit use of this software is permitted. No part of this software may be incorporated into a commercial product without the written consent of the authors.
• This software is provided "as is" with no warranties of any kind. The University of  Washington in St Louis disclaims all liability of any kind arising out of your use of, or misuse of, these tools and the information contained and referenced within them.
• You may modify or use the source code for other non-commercial, not-for-profit research endeavours, provided that all copyright attribution on the source code is retained, and the original or modified source code is not redistributed, in whole or in part, or included in or with any commercial product, except by written agreement with the authors, and full and complete attribution for use of the code is given in any resulting publications.
• Subject to these conditions, the software is provided free of charge to all interested parties.

  Contact Edson L. Horta edson-horta@ieee.org John W. Lockwood lockwood@arl.wustl.edu  

last updated:Mar 5, 2005  by edson-horta@ieee.org