Statistics Module
Introduction
The statistics module is capable of recording up to 256 different types of network events (such as packet arrivals, departures, and errors). Orginally designed to be interfaced with the Control Cell Processor (CCP), the statistics module could easily be modified to interface with other modules. The statistics module receives increment pulses and a corresponding counter number from an exterior component. This information is used to increment a 32-bit counter that is stored within two dualport Block RAMs located on the FPGA. Additionally, the statistics module provides a counter read interface so that the number of events for a specific counter number can be determined.
Cell Format
Up to four counter numbers can be read at a time. The counter number (address) is specified in bits 16 down to 9 of payloads 1, 3, 5, and 7. The corresponding counter data is returned in payloads 2, 4, 6, and 8. To inform the statistics read interface that an address is to be read, bit 31 of the corresponding address field is set. This indicates that the address is valid and the counter data should be returned. The cell format is shown below.
Use OpCode 0x"18" to perform a statistics read.
Documentation
Progress
- Block Diagrams Complete
- VHDL Coded
- Simulations Run
- Stat read interface added to CCP (opcode = 0x"18")
- Modified CCP simulated
- Place and Route run (Speed = 63.2 MHz)
- Tested in Hardware (success!)
- Removed SDRAM controller
- New Place and Route (Speed = 77.2 MHz)
- Added a 3rd pipeline stage to CCP_cntr.vhd to meet 100 MHz timing
FPX Homepage
Test
Snort Page
Last Modified July 30th, 2002 by mea1@arl.wustl.edu