The ATM switch being designed for this project uses a novel multicast architecture which is the only known architecture with optimal cost/performance as one scales up to large system sizes [TU93, TU94, DI94]. It uses a patented cell recycling scheme [U.S. Patent #5,402,415] to simultaneously achieve optimal scaling in switching network complexity, multicast routing memory and multicast virtual circuit reconfiguration time. This makes it the only multicast switch architecture suitable for the large scale switching systems needed for wide-scale deployment of multicast services.
The second major component of the project is an ATM Port Interconnect Chip (APIC) which is used for constructing flexible and extensible high performance host-network interfaces [DI94a, DI94b, DI95]. The APIC provides direct support for segmentation and reassembly, efficient transfer across a host processor's memory bus, support for zero-copy transfers to and from an application's address space and pacing of cell flows for individual virtual circuits.
A set of four integrated circuits is being designed for the project, operating at clock rates of up to 120 MHz. To achieve reliable chip-to-chip communication at these speeds using conventional CMOS technology, a novel, robust and area-efficient skew compensation circuit has been designed and will be used to accommodate variations in inter-chip wiring delays of up 25 ns. The circuit uses less area than a pad, is based on standard library components and is designed to operate under worst-case process and temperature conditions.
To ensure high throughput during overload, we have explored several techniques for maintaining packet integrity during overload. These studies have been documented in a recent report [TU95]. The report shows that by adding hysteresis to the standard early packet discard technique, it is possible to achieve 100% link efficiency during overload with a queue size equal to two maximum length packets. Hysteresis also increases the degree of fairness possible with early packet discard, in that virtual circuits operating at different rates experience approximately the same rate of packet loss. We have devised another variant of this technique which attempts to allocate the link capacity fairly (rather than the packet loss rate), but cannot yet report on its effectiveness.
Year 1995
Distributed
Imaging on Gigabit Networks.
Research on distributed imaging applications over gigabit networks and the underlying protocols and network technology needed to support those applications.
Gigabit ATM Applications Over 10 Gb/s SONET Ring.
Extension of gigabit network technology to operate over 10 Gb/s SONET metropolitan area network and demonstration of advanced applications on this facility. Supported by ARPA Technology Reinvestment Program.
APIC Talk given at the ARPA PI meeting in February, 1996.
Return to the ARL Home Page
Prepared by
Jonathan Turner: jst@cs.wustl.edu
Prepared 1/18/95,
Last Modified 7/18/96 by Diana Ehrlich.