Homework Assignment 3

Complete Homework

Submit Solutions to: Electronic Homework Server as a zip or tar file.

Now that you have designed a simple statistics module, it is time to code your design using VHDL.

Using VHDL, code your design, using stat_mod.vhd as your top level. Please adhere to the signal names given on the interface. This will simplify things later.
Here is the Coregen created cntr_ram.vhd description.
Keep in mind that:

You will eventually be putting this in hardware, so if you write synthesizable code now, MP1 will be very easy.
In hardware, you can't do everything in one clock cycle and achieve any reasonable speed. (Put some flops in your design, especially on the interface of block RAM).

All VHDL code you created (You may submit this/these as a .vhd file). (10 points)

Ok, now you've coded something, but will it work? In this section, we are going to simulate your design using ModelSim.

To perform this task, you must first compile your code. Download this makefile to compile your code and simulate your stat_mod component.
Type 'make compile' in a cygwin bash shell to compile your code. You will need to put the makefile in the sim directory.
If you have errors here, you will have to fix them before you proceed. Errors should be shown to you with the corresponding line error. Remember to add any files that you created to the makefile so that they will be compiled as well. (The makefile also assumes that there are separate directories for simulation and vhdl source code.)
Once your design compiles, you can begin simulating. Thoughtfully simulating your design can save hours later when testing in hardware. ALWAYS SIMULATE! A do file for simulating the interface can be found here. This can help debugging your design.
What to Turn In:

A Simulation Waveform using this do file. Note: you need only show the section of the waveform after the counters have been reset. (15 points)